[PATCH 2/3] MIPS: lantiq: fix setting the PCI bus speed on AR9

[John Crispin <blogic@openwrt.org>]

The bits used to set the PCI bus speed on AR9 are slightly different to those
used on Danube.

Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
---
 arch/mips/pci/pci-lantiq.c |    9 +++++++--
 1 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c
index 603d749..8656388 100644
--- a/arch/mips/pci/pci-lantiq.c
+++ b/arch/mips/pci/pci-lantiq.c
@@ -171,8 +171,13 @@ static int __devinit ltq_pci_startup(struct ltq_pci_data 
*conf)
        u32 temp_buffer;
 
        /* set clock to 33Mhz */
-       ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~0xf00000, LTQ_CGU_IFCCR);
-       ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | 0x800000, LTQ_CGU_IFCCR);
+       if (ltq_is_ar9()) {
+               ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~0x1f00000, 
LTQ_CGU_IFCCR);
+               ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | 0xe00000, 
LTQ_CGU_IFCCR);
+       } else {
+               ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~0xf00000, 
LTQ_CGU_IFCCR);
+               ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | 0x800000, 
LTQ_CGU_IFCCR);
+       }
 
        /* external or internal clock ? */
        if (conf->clock) {
-- 
1.7.2.3