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[PATCH 05/13] MIPS: ath79: add AR933X specific glue for ath79_device_res

To: Ralf Baechle <ralf@linux-mips.org>
Subject: [PATCH 05/13] MIPS: ath79: add AR933X specific glue for ath79_device_reset_{set,clear}
From: Gabor Juhos <juhosg@openwrt.org>
Date: Mon, 20 Jun 2011 21:26:05 +0200
Cc: linux-mips@linux-mips.org, Kathy Giori <kgiori@qca.qualcomm.com>, "Luis R. Rodriguez" <rodrigue@qca.qualcomm.com>, Gabor Juhos <juhosg@openwrt.org>
In-reply-to: <1308597973-6037-1-git-send-email-juhosg@openwrt.org>
References: <1308597973-6037-1-git-send-email-juhosg@openwrt.org>
Sender: linux-mips-bounce@linux-mips.org
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
---
 arch/mips/ath79/common.c                       |    4 ++++
 arch/mips/include/asm/mach-ath79/ar71xx_regs.h |    1 +
 2 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/mips/ath79/common.c b/arch/mips/ath79/common.c
index 58f60e7..38c2ad7 100644
--- a/arch/mips/ath79/common.c
+++ b/arch/mips/ath79/common.c
@@ -64,6 +64,8 @@ void ath79_device_reset_set(u32 mask)
                reg = AR724X_RESET_REG_RESET_MODULE;
        else if (soc_is_ar913x())
                reg = AR913X_RESET_REG_RESET_MODULE;
+       else if (soc_is_ar933x())
+               reg = AR933X_RESET_REG_RESET_MODULE;
        else
                BUG();
 
@@ -86,6 +88,8 @@ void ath79_device_reset_clear(u32 mask)
                reg = AR724X_RESET_REG_RESET_MODULE;
        else if (soc_is_ar913x())
                reg = AR913X_RESET_REG_RESET_MODULE;
+       else if (soc_is_ar933x())
+               reg = AR933X_RESET_REG_RESET_MODULE;
        else
                BUG();
 
diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h 
b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
index 418b739..c7159e3 100644
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -173,6 +173,7 @@
 
 #define AR724X_RESET_REG_RESET_MODULE          0x1c
 
+#define AR933X_RESET_REG_RESET_MODULE          0x1c
 #define AR933X_RESET_REG_BOOTSTRAP             0xac
 
 #define MISC_INT_ETHSW                 BIT(12)
-- 
1.7.2.1


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