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Re: [PATCH 07/11] MIPS: BCM63XX: change irq code to prepare for per-cpu

To: Maxime Bizon <mbizon@freebox.fr>
Subject: Re: [PATCH 07/11] MIPS: BCM63XX: change irq code to prepare for per-cpu peculiarity.
From: Jonas Gorski <jonas.gorski@gmail.com>
Date: Wed, 15 Jun 2011 14:54:11 +0200
Cc: ralf@linux-mips.org, linux-mips@linux-mips.org, florian@openwrt.org
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In-reply-to: <1307742441-28284-8-git-send-email-mbizon@freebox.fr>
References: <1307742441-28284-1-git-send-email-mbizon@freebox.fr> <1307742441-28284-8-git-send-email-mbizon@freebox.fr>
Sender: linux-mips-bounce@linux-mips.org
Hi,

On 10 June 2011 23:47, Maxime Bizon <mbizon@freebox.fr> wrote:
> diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h 
> b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
> index 3ea2681..4354be1 100644
> --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
> +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
> @@ -89,9 +89,18 @@
>
>  /* Interrupt Mask register */
>  #define PERF_IRQMASK_REG               0xc
> +#define PERF_IRQSTAT_REG               0x10

You are re-adding the duplicate PERF_IRQSTAT_REG I just removed.

> +#define PERF_IRQMASK_6338_REG          0xc
> +#define PERF_IRQMASK_6345_REG          0xc
> +#define PERF_IRQMASK_6348_REG          0xc
> +#define PERF_IRQMASK_6358_REG          0xc

If you are adding one for each SoC, why keep the "generic"
PERF_IRQMASK_REG at all? AFAICS it isn't used it any more.

>
>  /* Interrupt Status register */
>  #define PERF_IRQSTAT_REG               0x10
> +#define PERF_IRQSTAT_6338_REG          0x10
> +#define PERF_IRQSTAT_6345_REG          0x10
> +#define PERF_IRQSTAT_6348_REG          0x10
> +#define PERF_IRQSTAT_6358_REG          0x10

The same applies to the "generic" PERF_IRQSTAT_REG, you can also remove it.


Jonas

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