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Re: [PATCH 05/11] MIPS: BCM63XX: cleanup cpu registers.

To: Maxime Bizon <mbizon@freebox.fr>
Subject: Re: [PATCH 05/11] MIPS: BCM63XX: cleanup cpu registers.
From: Jonas Gorski <jonas.gorski@gmail.com>
Date: Wed, 15 Jun 2011 14:50:14 +0200
Cc: ralf@linux-mips.org, linux-mips@linux-mips.org, florian@openwrt.org
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Sender: linux-mips-bounce@linux-mips.org
Hi Maxime,

On 10 June 2011 23:47, Maxime Bizon <mbizon@freebox.fr> wrote:
> Use preprocessor when possible to avoid duplicated and error-prone
> code.
>
> Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
> ---
>  arch/mips/bcm63xx/cpu.c                          |  145 +----------
>  arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h |  311 
> +++++++---------------
>  2 files changed, 109 insertions(+), 347 deletions(-)
>
> diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c
> index 7c7e4d4..027ac30 100644
> --- a/arch/mips/bcm63xx/cpu.c
> +++ b/arch/mips/bcm63xx/cpu.c
> @@ -33,162 +33,37 @@ static unsigned int bcm63xx_memory_size;
>  * 6338 register sets and irqs
>  */
>  static const unsigned long bcm96338_regs_base[] = {

I would propose naming these bcm63??_regs_base; it would be more in
line with the rest of the code.

> -       [RSET_DSL_LMEM]         = BCM_6338_DSL_LMEM_BASE,
> -       [RSET_PERF]             = BCM_6338_PERF_BASE,
> -       [RSET_TIMER]            = BCM_6338_TIMER_BASE,
> -       [RSET_WDT]              = BCM_6338_WDT_BASE,
> -       [RSET_UART0]            = BCM_6338_UART0_BASE,
> -       [RSET_UART1]            = BCM_6338_UART1_BASE,
> -       [RSET_GPIO]             = BCM_6338_GPIO_BASE,
> -       [RSET_SPI]              = BCM_6338_SPI_BASE,
> -       [RSET_OHCI0]            = BCM_6338_OHCI0_BASE,
> -       [RSET_OHCI_PRIV]        = BCM_6338_OHCI_PRIV_BASE,
> -       [RSET_USBH_PRIV]        = BCM_6338_USBH_PRIV_BASE,
> -       [RSET_UDC0]             = BCM_6338_UDC0_BASE,
> -       [RSET_MPI]              = BCM_6338_MPI_BASE,
> -       [RSET_PCMCIA]           = BCM_6338_PCMCIA_BASE,
> -       [RSET_SDRAM]            = BCM_6338_SDRAM_BASE,
> -       [RSET_DSL]              = BCM_6338_DSL_BASE,
> -       [RSET_ENET0]            = BCM_6338_ENET0_BASE,
> -       [RSET_ENET1]            = BCM_6338_ENET1_BASE,
> -       [RSET_ENETDMA]          = BCM_6338_ENETDMA_BASE,
> -       [RSET_MEMC]             = BCM_6338_MEMC_BASE,
> -       [RSET_DDR]              = BCM_6338_DDR_BASE,
> +       __GEN_CPU_REGS_TABLE(6338)
>  };
>
>  static const int bcm96338_irqs[] = {
> -       [IRQ_TIMER]             = BCM_6338_TIMER_IRQ,
> -       [IRQ_UART0]             = BCM_6338_UART0_IRQ,
> -       [IRQ_DSL]               = BCM_6338_DSL_IRQ,
> -       [IRQ_ENET0]             = BCM_6338_ENET0_IRQ,
> -       [IRQ_ENET_PHY]          = BCM_6338_ENET_PHY_IRQ,
> -       [IRQ_ENET0_RXDMA]       = BCM_6338_ENET0_RXDMA_IRQ,
> -       [IRQ_ENET0_TXDMA]       = BCM_6338_ENET0_TXDMA_IRQ,
> +       __GEN_CPU_IRQ_TABLE(6338)
>  };
>
> -/*
> - * 6345 register sets and irqs
> - */

You should leave the comment here (or also delete the 6338 one on top).

>  static const unsigned long bcm96345_regs_base[] = {
> -       [RSET_DSL_LMEM]         = BCM_6345_DSL_LMEM_BASE,
> -       [RSET_PERF]             = BCM_6345_PERF_BASE,
> -       [RSET_TIMER]            = BCM_6345_TIMER_BASE,
> -       [RSET_WDT]              = BCM_6345_WDT_BASE,
> -       [RSET_UART0]            = BCM_6345_UART0_BASE,
> -       [RSET_UART1]            = BCM_6345_UART1_BASE,
> -       [RSET_GPIO]             = BCM_6345_GPIO_BASE,
> -       [RSET_SPI]              = BCM_6345_SPI_BASE,
> -       [RSET_UDC0]             = BCM_6345_UDC0_BASE,
> -       [RSET_OHCI0]            = BCM_6345_OHCI0_BASE,
> -       [RSET_OHCI_PRIV]        = BCM_6345_OHCI_PRIV_BASE,
> -       [RSET_USBH_PRIV]        = BCM_6345_USBH_PRIV_BASE,
> -       [RSET_MPI]              = BCM_6345_MPI_BASE,
> -       [RSET_PCMCIA]           = BCM_6345_PCMCIA_BASE,
> -       [RSET_DSL]              = BCM_6345_DSL_BASE,
> -       [RSET_ENET0]            = BCM_6345_ENET0_BASE,
> -       [RSET_ENET1]            = BCM_6345_ENET1_BASE,
> -       [RSET_ENETDMA]          = BCM_6345_ENETDMA_BASE,
> -       [RSET_EHCI0]            = BCM_6345_EHCI0_BASE,
> -       [RSET_SDRAM]            = BCM_6345_SDRAM_BASE,
> -       [RSET_MEMC]             = BCM_6345_MEMC_BASE,
> -       [RSET_DDR]              = BCM_6345_DDR_BASE,
> +       __GEN_CPU_REGS_TABLE(6345)
>  };
>
>  static const int bcm96345_irqs[] = {
> -       [IRQ_TIMER]             = BCM_6345_TIMER_IRQ,
> -       [IRQ_UART0]             = BCM_6345_UART0_IRQ,
> -       [IRQ_DSL]               = BCM_6345_DSL_IRQ,
> -       [IRQ_ENET0]             = BCM_6345_ENET0_IRQ,
> -       [IRQ_ENET_PHY]          = BCM_6345_ENET_PHY_IRQ,
> -       [IRQ_ENET0_RXDMA]       = BCM_6345_ENET0_RXDMA_IRQ,
> -       [IRQ_ENET0_TXDMA]       = BCM_6345_ENET0_TXDMA_IRQ,
> +       __GEN_CPU_IRQ_TABLE(6345)
>  };
>
> -/*
> - * 6348 register sets and irqs
> - */

Same comment comment.

>  static const unsigned long bcm96348_regs_base[] = {
> -       [RSET_DSL_LMEM]         = BCM_6348_DSL_LMEM_BASE,
> -       [RSET_PERF]             = BCM_6348_PERF_BASE,
> -       [RSET_TIMER]            = BCM_6348_TIMER_BASE,
> -       [RSET_WDT]              = BCM_6348_WDT_BASE,
> -       [RSET_UART0]            = BCM_6348_UART0_BASE,
> -       [RSET_UART1]            = BCM_6348_UART1_BASE,
> -       [RSET_GPIO]             = BCM_6348_GPIO_BASE,
> -       [RSET_SPI]              = BCM_6348_SPI_BASE,
> -       [RSET_OHCI0]            = BCM_6348_OHCI0_BASE,
> -       [RSET_OHCI_PRIV]        = BCM_6348_OHCI_PRIV_BASE,
> -       [RSET_USBH_PRIV]        = BCM_6348_USBH_PRIV_BASE,
> -       [RSET_MPI]              = BCM_6348_MPI_BASE,
> -       [RSET_PCMCIA]           = BCM_6348_PCMCIA_BASE,
> -       [RSET_SDRAM]            = BCM_6348_SDRAM_BASE,
> -       [RSET_DSL]              = BCM_6348_DSL_BASE,
> -       [RSET_ENET0]            = BCM_6348_ENET0_BASE,
> -       [RSET_ENET1]            = BCM_6348_ENET1_BASE,
> -       [RSET_ENETDMA]          = BCM_6348_ENETDMA_BASE,
> -       [RSET_MEMC]             = BCM_6348_MEMC_BASE,
> -       [RSET_DDR]              = BCM_6348_DDR_BASE,
> +       __GEN_CPU_REGS_TABLE(6348)
>  };
>
>  static const int bcm96348_irqs[] = {
> -       [IRQ_TIMER]             = BCM_6348_TIMER_IRQ,
> -       [IRQ_UART0]             = BCM_6348_UART0_IRQ,
> -       [IRQ_DSL]               = BCM_6348_DSL_IRQ,
> -       [IRQ_ENET0]             = BCM_6348_ENET0_IRQ,
> -       [IRQ_ENET1]             = BCM_6348_ENET1_IRQ,
> -       [IRQ_ENET_PHY]          = BCM_6348_ENET_PHY_IRQ,
> -       [IRQ_OHCI0]             = BCM_6348_OHCI0_IRQ,
> -       [IRQ_PCMCIA]            = BCM_6348_PCMCIA_IRQ,
> -       [IRQ_ENET0_RXDMA]       = BCM_6348_ENET0_RXDMA_IRQ,
> -       [IRQ_ENET0_TXDMA]       = BCM_6348_ENET0_TXDMA_IRQ,
> -       [IRQ_ENET1_RXDMA]       = BCM_6348_ENET1_RXDMA_IRQ,
> -       [IRQ_ENET1_TXDMA]       = BCM_6348_ENET1_TXDMA_IRQ,
> -       [IRQ_PCI]               = BCM_6348_PCI_IRQ,
> +       __GEN_CPU_IRQ_TABLE(6348)
> +
>  };
>
> -/*
> - * 6358 register sets and irqs
> - */

Same comment comment.


Jonas
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