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Re: [PATCH] tty: 8250: handle USR for DesignWare 8250 with correct acces

To: Shane McDonald <mcdonald.shane@gmail.com>
Subject: Re: [PATCH] tty: 8250: handle USR for DesignWare 8250 with correct accessors
From: Jamie Iles <jamie@jamieiles.com>
Date: Wed, 15 Jun 2011 09:49:59 +0100
Cc: Ralf Baechle <ralf@linux-mips.org>, Jamie Iles <jamie@jamieiles.com>, linux-serial@vger.kernel.org, Greg Kroah-Hartman <gregkh@suse.de>, linux-mips@linux-mips.org, Marc St-Jean <bluezzer@gmail.com>, Anoop P A <anoop.pa@gmail.com>
In-reply-to: <BANLkTi=0Pk-2YT=jLeBTNLYELfo+e-saZA@mail.gmail.com>
References: <1307616525-22028-1-git-send-email-jamie@jamieiles.com> <20110610035817.GA6740@linux-mips.org> <BANLkTi=0Pk-2YT=jLeBTNLYELfo+e-saZA@mail.gmail.com>
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On Tue, Jun 14, 2011 at 09:33:45AM -0600, Shane McDonald wrote:
> On Thu, Jun 9, 2011 at 9:58 PM, Ralf Baechle <ralf@linux-mips.org> wrote:
> > If you look at arch/mips/include/asm/pmc-sierra/msp71xx/msp_regs.h there's
> >
> > #define MSP_UART0_BASE          (MSP_SLP_BASE + 0x100)
> >                                        /* UART0 controller base        */
> > #define MSP_BCPY_CTRL_BASE      (MSP_SLP_BASE + 0x120)
> >                                        /* Block Copy controller base   */
> >
> > So there are just 0x20 of address space reserved for that UART.  Me thinks
> > that PMC-Sierra clamped the 256 byte address space of the DesignWare APB
> > UART to what is standard for 16550 class UARTs, 8 registers which at a
> > shift of 4 is 0x20 bytes and the status register being accesses is really
> > something else.  I'd guess PMC-Sierra just remapped the register to
> > another address.
> 
> I have confirmed with a contact at PMC-Sierra that this is the case.

Thanks for confirming that Shane.  I'm currently working on a series to 
move the DesignWare handling code into the pmc-sierra platform and kill 
off UPIO_DWAPB{,32} and will post it in a couple of days.

Jamie

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