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Re: [PATCH] tty: 8250: handle USR for DesignWare 8250 with correct acces

To: Ralf Baechle <>
Subject: Re: [PATCH] tty: 8250: handle USR for DesignWare 8250 with correct accessors
From: Shane McDonald <>
Date: Tue, 14 Jun 2011 09:33:45 -0600
Cc: Jamie Iles <>,, Greg Kroah-Hartman <>,, Marc St-Jean <>, Anoop P A <>
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On Thu, Jun 9, 2011 at 9:58 PM, Ralf Baechle <> wrote:
> If you look at arch/mips/include/asm/pmc-sierra/msp71xx/msp_regs.h there's
> #define MSP_UART0_BASE          (MSP_SLP_BASE + 0x100)
>                                        /* UART0 controller base        */
> #define MSP_BCPY_CTRL_BASE      (MSP_SLP_BASE + 0x120)
>                                        /* Block Copy controller base   */
> So there are just 0x20 of address space reserved for that UART.  Me thinks
> that PMC-Sierra clamped the 256 byte address space of the DesignWare APB
> UART to what is standard for 16550 class UARTs, 8 registers which at a
> shift of 4 is 0x20 bytes and the status register being accesses is really
> something else.  I'd guess PMC-Sierra just remapped the register to
> another address.

I have confirmed with a contact at PMC-Sierra that this is the case.


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