Re: [PATCH] tty: 8250: handle USR for DesignWare 8250 with correct accessors

[Shane McDonald <mcdonald.shane@gmail.com>]

On Thu, Jun 9, 2011 at 9:58 PM, Ralf Baechle <ralf@linux-mips.org> wrote:
> On Thu, Jun 09, 2011 at 11:48:45AM +0100, Jamie Iles wrote:
>
> The original read access was for a read access at offset 0xc0 from the
> base address.  Your patch changes this to offset 0x1f * 4 = 0x7c.
>
> If you look at arch/mips/include/asm/pmc-sierra/msp71xx/msp_regs.h there's
>
> #define MSP_UART0_BASE          (MSP_SLP_BASE + 0x100)
>                                        /* UART0 controller base        */
> #define MSP_BCPY_CTRL_BASE      (MSP_SLP_BASE + 0x120)
>                                        /* Block Copy controller base   */
>
> So there are just 0x20 of address space reserved for that UART.  Me thinks
> that PMC-Sierra clamped the 256 byte address space of the DesignWare APB
> UART to what is standard for 16550 class UARTs, 8 registers which at a
> shift of 4 is 0x20 bytes and the status register being accesses is really
> something else.  I'd guess PMC-Sierra just remapped the register to
> another address.
...
> On a 2nd thought I wonder if the restricted address space of the PMC-Sierra
> variant and the strange remapping would justify treating it as a subvariant
> of the DW APB UART, rename it to UPIO_PMC_MSP_DWAPB, hardcode the access to
> the remapped status register.  And get rid of the unused UPIO_DWAPB32 ...
>
> I've cced a few people who should know more about this.

Marc and I were originally responsible for this code, but we're no longer
at PMC-Sierra, and I don't remember the details.  If Anoop isn't able
confirm Ralf's suspicions regarding the smaller address space
and remapped register, I'll see if I can track down some former co-workers
that could shed some light on this.

Ralf's 2nd thought makes perfect sense to me, though.

Shane