linux-mips
[Top] [All Lists]

[PATCH v4 1/5] MIPS: Add accessor macros for 64-bit performance counter

To: linux-mips@linux-mips.org, ralf@linux-mips.org
Subject: [PATCH v4 1/5] MIPS: Add accessor macros for 64-bit performance counter registers.
From: David Daney <ddaney@caviumnetworks.com>
Date: Fri, 20 May 2011 14:39:18 -0700
Cc: David Daney <ddaney@caviumnetworks.com>
In-reply-to: <1305927562-30351-1-git-send-email-ddaney@caviumnetworks.com>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <1305927562-30351-1-git-send-email-ddaney@caviumnetworks.com>
Sender: linux-mips-bounce@linux-mips.org
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
 arch/mips/include/asm/mipsregs.h |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index a1f0f32..2619900 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -1019,18 +1019,26 @@ do {                                                    
                \
 #define write_c0_perfctrl0(val)        __write_32bit_c0_register($25, 0, val)
 #define read_c0_perfcntr0()    __read_32bit_c0_register($25, 1)
 #define write_c0_perfcntr0(val)        __write_32bit_c0_register($25, 1, val)
+#define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1)
+#define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
 #define read_c0_perfctrl1()    __read_32bit_c0_register($25, 2)
 #define write_c0_perfctrl1(val)        __write_32bit_c0_register($25, 2, val)
 #define read_c0_perfcntr1()    __read_32bit_c0_register($25, 3)
 #define write_c0_perfcntr1(val)        __write_32bit_c0_register($25, 3, val)
+#define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3)
+#define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
 #define read_c0_perfctrl2()    __read_32bit_c0_register($25, 4)
 #define write_c0_perfctrl2(val)        __write_32bit_c0_register($25, 4, val)
 #define read_c0_perfcntr2()    __read_32bit_c0_register($25, 5)
 #define write_c0_perfcntr2(val)        __write_32bit_c0_register($25, 5, val)
+#define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5)
+#define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
 #define read_c0_perfctrl3()    __read_32bit_c0_register($25, 6)
 #define write_c0_perfctrl3(val)        __write_32bit_c0_register($25, 6, val)
 #define read_c0_perfcntr3()    __read_32bit_c0_register($25, 7)
 #define write_c0_perfcntr3(val)        __write_32bit_c0_register($25, 7, val)
+#define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7)
+#define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
 
 /* RM9000 PerfCount performance counter register */
 #define read_c0_perfcount()    __read_64bit_c0_register($25, 0)
-- 
1.7.2.3


<Prev in Thread] Current Thread [Next in Thread>