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Re: System suffers frequent TLB miss

To: "wilbur.chan" <wilbur512@gmail.com>
Subject: Re: System suffers frequent TLB miss
From: "Jayachandran C." <jayachandranc@netlogicmicro.com>
Date: Mon, 4 Apr 2011 23:12:14 +0530
Cc: Linux MIPS Mailing List <linux-mips@linux-mips.org>
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On Sun, Apr 03, 2011 at 11:49:13AM +0800, wilbur.chan wrote:
> Hi all
> 
> We have a system running on mips64 xlr 732.  Our major application
[...]
> I'm  totally exhausted about the tlb miss, I wonder if we can record
> the virtual region of tlb miss  and the miss count in each region, in
> that way,
> 
> I can find out which part leads to this tlb miss.That is , to record
> C0_BADVADDR  in tlb miss.
> 
> 
> However I'm not sure how to add code in build_r4000_tlb_refill_handler
> function, for it is wrote in some strage way .
> 
> Any  suggestion on how to reduce tlb miss?

In our SDK linux, there is some code to add instructions in the TLB 
exception handler using the cpu scratch registers to count TLB misses.
(see mips/mm/tlbex.c code generated with OS_SCRATCH_REG2)

You can extend it with another scratch register containing the an address
per cpu where to record TLB miss badvaddr values(you would just need to 
add code to add sizeof(void*) to the scratch reg value and UASM_i_SW to
store addr). This should give you and idea which adresses are causing the
TLB miss.

I have not actually tried this out on linux(but I have implemented similar
code on FreeBSD and vxWorks) so it should work, let me know if you are
able to get this going...

JC.

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