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Re: [patch 2/3] MIPS: Octeon: Rewrite interrupt handling code.

To: Thomas Gleixner <tglx@linutronix.de>
Subject: Re: [patch 2/3] MIPS: Octeon: Rewrite interrupt handling code.
From: David Daney <ddaney@caviumnetworks.com>
Date: Mon, 28 Mar 2011 14:55:51 -0700
Cc: Ralf Baechle <ralf@linux-mips.org>, linux-mips@linux-mips.org
In-reply-to: <20110328150627.679291180@linutronix.de>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20110328150330.110780523@linutronix.de> <20110328150627.679291180@linutronix.de>
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On 03/28/2011 08:06 AM, Thomas Gleixner wrote:
From: David Daney<ddaney@caviumnetworks.com>

This includes conversion to new style irq_chip functions, and
correctly enabling/disabling per-CPU interrupts.

The hardware interrupt bit to irq number mapping is now done with a
flexible map, instead of by bit twiddling the irq number.

[ tglx: Adjusted to new irq_cpu_on/offline callbacks and
         __irq_set_affinity_lock ]

Signed-off-by: David Daney<ddaney@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Cc: ralf@linux-mips.org
LKML-Reference:<1301081931-11240-5-git-send-email-ddaney@caviumnetworks.com>
Signed-off-by: Thomas Gleixner<tglx@linutronix.de>
---
  arch/mips/cavium-octeon/octeon-irq.c           | 1410 
++++++++++++++-----------
  arch/mips/cavium-octeon/setup.c                |   12
  arch/mips/cavium-octeon/smp.c                  |   39
  arch/mips/include/asm/mach-cavium-octeon/irq.h |  243 +---
  arch/mips/include/asm/octeon/octeon.h          |    2
  arch/mips/pci/msi-octeon.c                     |   20
  6 files changed, 915 insertions(+), 811 deletions(-)


Well tglx modified my patch slightly, but it still works. So this one is OK too.

David Daney

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