[Top] [All Lists]

Re: [patch 2/3] MIPS: Octeon: Rewrite interrupt handling code.

To: Thomas Gleixner <>
Subject: Re: [patch 2/3] MIPS: Octeon: Rewrite interrupt handling code.
From: David Daney <>
Date: Mon, 28 Mar 2011 14:55:51 -0700
Cc: Ralf Baechle <>,
In-reply-to: <>
Original-recipient: rfc822;
References: <> <>
User-agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv: Gecko/20101027 Fedora/3.0.10-1.fc12 Thunderbird/3.0.10
On 03/28/2011 08:06 AM, Thomas Gleixner wrote:
From: David Daney<>

This includes conversion to new style irq_chip functions, and
correctly enabling/disabling per-CPU interrupts.

The hardware interrupt bit to irq number mapping is now done with a
flexible map, instead of by bit twiddling the irq number.

[ tglx: Adjusted to new irq_cpu_on/offline callbacks and
         __irq_set_affinity_lock ]

Signed-off-by: David Daney<>
Signed-off-by: Thomas Gleixner<>
  arch/mips/cavium-octeon/octeon-irq.c           | 1410 
  arch/mips/cavium-octeon/setup.c                |   12
  arch/mips/cavium-octeon/smp.c                  |   39
  arch/mips/include/asm/mach-cavium-octeon/irq.h |  243 +---
  arch/mips/include/asm/octeon/octeon.h          |    2
  arch/mips/pci/msi-octeon.c                     |   20
  6 files changed, 915 insertions(+), 811 deletions(-)

Well tglx modified my patch slightly, but it still works. So this one is OK too.

David Daney

<Prev in Thread] Current Thread [Next in Thread>