When a CPU is brought on-line, per-CPU interrupts need to be enabled
on the new CPU. The local timer and things like perf counters that
rely on interrupts don't work if their interrupts are not enabled.
Likewise when a CPU is taken off-line, we may need to clean up the
I solve both of these problems by adding a pair of function pointers
to the irq_chip structure, along with some simple helper functions to
When the CPU is being brought on-line, but before interrupts are
enabled, I iterate through all possible IRQs and invoke their
irq_cpu_online() hooks. Most of these are null, so are not called,
but my per-CPU IRQs do have hooks and the corresponding signals are
routed to the new CPU.
There are two patches here.
1) Changes to the core irq code.
2) My SOC/Board interrupt handling rewrite that uses the new
David Daney (2):
genirq: Add chip hooks for taking CPUs on/off line.
MIPS: Octeon: Rewrite interrupt handling code.
arch/mips/Kconfig | 1 +
arch/mips/cavium-octeon/octeon-irq.c | 1388 ++++++++++++++----------
arch/mips/cavium-octeon/setup.c | 12 -
arch/mips/cavium-octeon/smp.c | 39 +-
arch/mips/include/asm/mach-cavium-octeon/irq.h | 243 ++---
arch/mips/include/asm/octeon/octeon.h | 2 +
arch/mips/pci/msi-octeon.c | 20 +-
include/linux/irq.h | 8 +
include/linux/irqdesc.h | 6 +
kernel/irq/chip.c | 35 +
10 files changed, 968 insertions(+), 786 deletions(-)