| To: | Ray Will <hustos@gmail.com> |
|---|---|
| Subject: | Re: merge two insts into one in a time sensitive routing |
| From: | Ralf Baechle <ralf@linux-mips.org> |
| Date: | Tue, 25 Jan 2011 14:36:40 +0100 |
| Cc: | linux-mips@linux-mips.org, linux-mm@vger.kernel.org |
| In-reply-to: | <AANLkTikSRmSpU+8FXOnqQ8Xm=ms=SZdrj=7WN3SLPVuJ@mail.gmail.com> |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <AANLkTikSRmSpU+8FXOnqQ8Xm=ms=SZdrj=7WN3SLPVuJ@mail.gmail.com> |
| Sender: | linux-mips-bounce@linux-mips.org |
| User-agent: | Mutt/1.5.21 (2010-09-15) |
On Tue, Jan 25, 2011 at 05:04:01PM +0800, Ray Will wrote: > The following two lines should be merged into one inst. It is the tlb > refill handler, quite time sensitive. > 569 uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16); > 570 uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff); > > Merged to > uasm_i_lui(p, tmp, ((PM_HUGE_MASK & 0xffff) | (PM_HUGE_MASK >> 16)); With 4K pages (=> 1M huge pages) we'd want the value 0x001fe000 to be loaded. Your change results in in a LUI $tmp, 0xe01f instruction being generated and that's an illegal value for the c0_pagemask register so the operation is now architecturally undefined. Similar for other page sizes. All possible values for PM_HUGE_MASK will have bits set in the upper and lower 16 halves of the register so there will always two instructions be required to load the pagemask value. Ralf |
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