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Re: 24k data cache, PIPT or VIPT?

To: "Edgar E. Iglesias" <edgar.iglesias@axis.com>
Subject: Re: 24k data cache, PIPT or VIPT?
From: Ralf Baechle <ralf@linux-mips.org>
Date: Sun, 23 Jan 2011 19:11:13 +0100
Cc: COLin <colin@realtek.com>, "linux-mips@linux-mips.org" <linux-mips@linux-mips.org>
In-reply-to: <20110123043439.GA20840@laped.lan>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <AB43F607AA1BE0439402E9061AC9519D011EF513EB8D@rtitmbs7.realtek.com.tw> <20110123043439.GA20840@laped.lan>
Resent-date: Mon, 24 Jan 2011 15:13:22 +0100
Resent-from: Ralf Baechle <ralf@linux-mips.org>
Resent-message-id: <20110124141322.GC31933@linux-mips.org>
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On Sun, Jan 23, 2011 at 05:34:39AM +0100, Edgar E. Iglesias wrote:

> This line is confusing:
> "This bit is only set if the data cache config and MMU type would normally 
> cause aliasing"
> 
> because I don't know what they mean by "normally".

Normally means the behaviour expected from a text book implementation of a
VIPT cache.

  Ralf

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