| To: | David Daney <ddaney@caviumnetworks.com> |
|---|---|
| Subject: | Re: [PATCH 2/2] MIPS: Optimize TLB handlers for Octeon CPUs |
| From: | Jonas Gorski <jonas.gorski@gmail.com> |
| Date: | Wed, 19 Jan 2011 21:44:47 +0100 |
| Cc: | linux-mips@linux-mips.org, ralf@linux-mips.org |
| Dkim-signature: | v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc:content-type; bh=uFXEAugw2BaHWUDOHGQ2xU4pCi4V9z4Jo/QS9V2St1k=; b=AwU0doBvk1QWBifGSF6yyjIGQ3kBnB2VaeO3lK0yagVS8Qy9f6QJe1WpUwkh5WY7sN RSLa754oksvIghT5Avfz+YHuAEqCr9GfMblJ9Gi8e3xJttV+mlDNRVIbg63hLh2rNlgj vz90QhZd4sZcWXA1xYQJs7KHUN9ukkMF3FsE0= |
| Domainkey-signature: | a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type; b=UCphZkeghW5ZGD1ImCeBQlYu1ek5TIMSlNcpwisthOGdAUj4DuoqKsYriWSmp9MUzw k9zZztL4uVIHctYC24NzmePASJCs3QSYyS8C4lgKSX/V5iihaEQqbBg5h/GmZPQX/oNg jhDz7hvan/XDZ9hbwSCfzLhzwWooqyToK5WJU= |
| In-reply-to: | <4D3743FF.1080201@caviumnetworks.com> |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <1293502077-9196-1-git-send-email-ddaney@caviumnetworks.com> <1293502077-9196-3-git-send-email-ddaney@caviumnetworks.com> <AANLkTinZZ2TziwkiBfhqV-3-VfXwU+EPx3OHsnTRVChT@mail.gmail.com> <4D373E5B.5010303@caviumnetworks.com> <AANLkTi=aZSwQCVudjZrUoOZYGJscER8R3vOsRcgadw-_@mail.gmail.com> <4D3743FF.1080201@caviumnetworks.com> |
| Sender: | linux-mips-bounce@linux-mips.org |
On 19/01/2011, David Daney <ddaney@caviumnetworks.com> wrote: > It is a bug in GCC-4.3. The proper fix is to add 'return 0;' after that > BUG() statement. > > I will prepare a patch. Yes, that works. Thanks for the quick response. Jonas |
| <Prev in Thread] | Current Thread | [Next in Thread> |
|---|---|---|
| ||
| Previous by Date: | Re: [PATCH 2/2] MIPS: Optimize TLB handlers for Octeon CPUs, David Daney |
|---|---|
| Next by Date: | [PATCH] MIPS: Add an unreachable return statement to satisfy buggy GCCs., David Daney |
| Previous by Thread: | Re: [PATCH 2/2] MIPS: Optimize TLB handlers for Octeon CPUs, David Daney |
| Next by Thread: | [PATCH] MIPS: Add an unreachable return statement to satisfy buggy GCCs., David Daney |
| Indexes: | [Date] [Thread] [Top] [All Lists] |