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Re: SMTC support status in latest git head.

To: "Kevin D. Kissell" <kevink@paralogos.com>
Subject: Re: SMTC support status in latest git head.
From: Anoop P A <anoop.pa@gmail.com>
Date: Fri, 07 Jan 2011 01:53:16 +0530
Cc: STUART VENTERS <stuart.venters@adtran.com>, "Anoop P.A." <Anoop_P.A@pmc-sierra.com>, linux-mips@linux-mips.org
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On Wed, 2011-01-05 at 11:23 -0800, Kevin D. Kissell wrote:
> >             LONG_S  $5, PT_R5(sp)
> >             LONG_S  v1, PT_STATUS(sp)
> 
> That's exactly what I'd propose as the cleanest minimal fix.  I've got a 
> version that also replaces the .set mips32 / .set mips0 with the .set 
> push / .set pop paradigm, which I'd have used in the original code if 
> I'd known at the time about that assembler directive.  I'm hoping to be 
> able to test on a Malta/34K reference platform, and make sure there 
> isn't breakage on that platform branch as well, before we commit to the 
> repository.

I hope somebody can test this patch on Malta/34K platform. I don't have
access to any malta boards and I believe 34K MT simulations is not
available on qemu.

> 
> Your msp_smtc.c file looks plausible on the face of it.  The 
> init_secondary function has the quirk that it expects to execute on each 
> "CPU" in numerical order, which is very likely but not guaranteed. It 
> *ought* to be harmless in the rare case where it fails, but the 
> assumption is worth a comment, IMHO.
Yes I will add a comment. 

> 
> At this point, there shouldn't be a whole lot of SMTC-specific mystery 
> to get your timer running on the second VPE.  You know it's taking 
> interrupts, because of the IPIs getting through, so in principle you 
> just need to run the chain of enables from the clock peripheral itself 
> through the CIC to the CPU core and the IM bits.

I hope we are almost there. I have made some progress with the debug . I
think you should be able to give better insight to the observation I
have made.

1. Without selecting CONFIG_MIPS_MT_SMTC_IM_BACKSTOP My kernel hangs in
calibration loop itself . ( I haven't looked further into this).

2. With CONFIG_MIPS_MT_SMTC_IM_BACKSTOP I found I am getting 3
VPE1-TIMER interrupt ( one for each TC of VPE1) .However this interrupts
are not getting carried till c0_compare_interrupt . 

do_IRQ call had a SMTC hook which is modifying tccontext ( To reduce
complexity I haven't selected SMTC affinity). 

Once I disabled this call . I am seeing VPE1 timer interrupts and able
to boot completely without any issue's so far :).

/ # cat /proc/interrupts
           CPU0       CPU1       CPU2       CPU3       CPU4       CPU5
CPU6
  1:        171     727459     727561     727533         27     727446
727453            MIPS  SMTC_IPI
  6:          0          0          0          0          0          0
0            MIPS  MSP CIC cascade
  8:          0          0          0          0          0          0
0         MSP_CIC  Softreset button
  9:          0          0          0          0          0          0
0         MSP_CIC  Standby switch
 21:          0          0          0          0          0          0
0         MSP_CIC  MSP PER cascade
 25:     727507        484         11          0          0          0
0         MSP_CIC  timer
 27:          0          0          0          0        258         10
1         MSP_CIC  serial
 34:          0          0          0          0     727533          7
1         MSP_CIC  timer


BTW following code in my cic init was setting hwmask.

        /* initialize all the IRQ descriptors */
        for (i = MSP_CIC_INTBASE ; i < MSP_CIC_INTBASE + 32 ; i++) {
                set_irq_chip_and_handler(i, &msp_cic_irq_controller,
                                         handle_level_irq);
#ifdef CONFIG_MIPS_MT_SMTC
                irq_hwmask[i] = C_IRQ4;
#endif
        }



> It would be really cool if we could get a stable repository branch that 
> boots SMTC out-of-the-box on both Malta and the MSP platform.
:)

> 
>              Regards,
> 
>              Kevin K.
> 
> 
Thanks
Anoop


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