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Re: [PATCH 2/2] MIPS: Use BBIT instructions in TLB handlers

To: David Daney <ddaney@caviumnetworks.com>
Subject: Re: [PATCH 2/2] MIPS: Use BBIT instructions in TLB handlers
From: Ralf Baechle <ralf@linux-mips.org>
Date: Tue, 28 Dec 2010 18:00:03 +0100
Cc: linux-mips@linux-mips.org
In-reply-to: <1292889290-12849-3-git-send-email-ddaney@caviumnetworks.com>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <1292889290-12849-1-git-send-email-ddaney@caviumnetworks.com> <1292889290-12849-3-git-send-email-ddaney@caviumnetworks.com>
Sender: linux-mips-bounce@linux-mips.org
User-agent: Mutt/1.5.21 (2010-09-15)
On Mon, Dec 20, 2010 at 03:54:50PM -0800, David Daney wrote:

> If the CPU supports BBIT0 and BBIT1, use them in TLB handlers as they
> are more efficient than an AND followed by an branch and then
> restoring the clobbered register.

Queued for 2.6.38.  Thanks,

  Ralf

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