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Re: SMTC support status in latest git head.

To: "Anoop P.A." <Anoop_P.A@pmc-sierra.com>
Subject: Re: SMTC support status in latest git head.
From: Ralf Baechle <ralf@linux-mips.org>
Date: Thu, 9 Dec 2010 17:07:48 +0000
Cc: linux-mips@linux-mips.org, "Kevin D. Kissell" <kevink@paralogos.com>
In-reply-to: <A7DEA48C84FD0B48AAAE33F328C02014033DADDA@BBY1EXM11.pmc_nt.nt.pmc-sierra.bc.ca>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <A7DEA48C84FD0B48AAAE33F328C02014033DADDA@BBY1EXM11.pmc_nt.nt.pmc-sierra.bc.ca>
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On Wed, Dec 08, 2010 at 05:48:48AM -0800, Anoop P.A. wrote:

> Any body is aware of SMTC support status in latest git sources?. I have tried 
> testing SMTC kernel for malta in qemu / OVP without any success ( emulators 
> not working for 34k). 

Correct.  MTI's MIPSsim is the only simulator that supports multithreading
afaik.

SMTC is not terribly popular so doesn't receive the regular testing it should
because it's also a complex beast.

> I am trying to bring up SMTC Linux support for an mips34K based soc ( MSP71xx 
> family).
> 
> While booting , kernel getting hung on calibrate loop delay. I am getting 
> only one interrupt from timer. With similar smtc platform support file (  
> changed to map smp_ops structure)  2.6.24-stable branch kernel ( where latest 
> timer structure introduced) boots fine. 

Timer interrupts work differently in SMTC.  Each CPU needs a clock event
device, that is an interrupt timer but the CPU core is restricted to just
one per VPE so in typical SMTC setup multiple CPUs aka TCs will have to
share an interrupt timer.  The way this works is that one of the TCs
associated with a VPE will take the timer interrupt and forward it to
the other TCs associated with the same VPE (if any) through a software
IPI mechanism.  The race conditions that need to handled to make this
work are ...  interesting.  Your problem seems to be simpler as you only
get a single timer interrupt.

  Ralf

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