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Re: [PATCH] MIPS: ASID conflict after CPU hotplug

To: Ralf Baechle <ralf@linux-mips.org>
Subject: Re: [PATCH] MIPS: ASID conflict after CPU hotplug
From: Maksim Rayskiy <maksim.rayskiy@gmail.com>
Date: Mon, 22 Nov 2010 10:38:50 -0800
Cc: "Kevin D. Kissell" <kevink@paralogos.com>, linux-mips@linux-mips.org
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On Sun, Nov 21, 2010 at 7:41 PM, Ralf Baechle <ralf@linux-mips.org> wrote:
> Unfortunately I haven't yet found a BMIPS board or manual in my mailbox
> so I can't really give a definitate answer.  But let me describe how
> the MIPS34K handles it.
>
> The 34K supports two TLB modes, shared and split TLB.  The VSMP kernel
> uses the TLB in split mode in which half of the TLB entries is available
> to each of the two threads aka VPEs.  So with a 64 entry TLB that's 32
> entries per VPE then.  Each VPE (or rather TC but see further down) has
> it's own c0_entryhi register, thus it's own ASID.  So no ASID collisions
> possible, ever.  This is the same as on a conventional SMP system where
> TLB and ASID number space are also per CPU.
>
> The SMTC kernel model (usually) uses the shared model, that is all the 64
> entries are now available to all threads and the ASID space is shared.
> This means allocation of the same ASID to multiple TCs needs to be avoided.
>
> It seems BMIPS falls into the latter class?
>

No, each thread has a separate TLB and all TLB-related registers are
also per thread. The conflict I have found was the same ASID for two
different processes on the second TP.

I still do not understand all the details, but what I saw was after
the second TP is brought back online init process runs on (migrates to
?) it with entryHi=1. If it tries to spawn another process, the child
gets the same ASID, because current asid_cache value is 0 (well it is
actually 0x100, but only lower 8 bits matter).

> Need to think a little about potencial consequences of your suggested
> patch.  It seems ok.  Kevin, what do you think?
>
>  Ralf
>

Thanks,
Maksim.

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