On Thu, 2010-11-18 at 06:56 +0000, Deng-Cheng Zhu wrote:
> Ignore events that are not for this PMU or are in off/error state.
Sorry I didn't see this before, thanks for pointing out that you
had included it for MIPS.
> Signed-off-by: Deng-Cheng Zhu <firstname.lastname@example.org>
> arch/mips/kernel/perf_event.c | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
> diff --git a/arch/mips/kernel/perf_event.c b/arch/mips/kernel/perf_event.c
> index 1ee44a3..9c6442a 100644
> --- a/arch/mips/kernel/perf_event.c
> +++ b/arch/mips/kernel/perf_event.c
> @@ -486,7 +486,7 @@ static int validate_event(struct cpu_hw_events *cpuc,
> struct hw_perf_event fake_hwc = event->hw;
> - if (event->pmu && event->pmu != &pmu)
> + if (event->pmu != &pmu || event->state <= PERF_EVENT_STATE_OFF)
> return 0;
> return mipspmu->alloc_counter(cpuc, &fake_hwc) >= 0;
So this is the opposite of what we're doing on ARM. Our
approach is to ignore events that are OFF (or in the ERROR
state) or that belong to a different PMU. We do this by
allowing them to *pass* validation (i.e. by returning 1 above).
This means that we won't unconditionally fail a mixed event group.
x86 does something similar in the collect_events function.