| To: | Will Deacon <will.deacon@arm.com> |
|---|---|
| Subject: | Re: [PATCH 5/5] MIPS/Perf-events: Use unsigned delta for right shift in event update |
| From: | Deng-Cheng Zhu <dengcheng.zhu@gmail.com> |
| Date: | Fri, 19 Nov 2010 15:16:38 +0800 |
| Cc: | ralf@linux-mips.org, a.p.zijlstra@chello.nl, fweisbec@gmail.com, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, wuzhangjin@gmail.com, paulus@samba.org, mingo@elte.hu, acme@redhat.com |
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| In-reply-to: | <1290072458.18450.1.camel@e102144-lin.cambridge.arm.com> |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <1290063401-25440-1-git-send-email-dengcheng.zhu@gmail.com> <1290063401-25440-6-git-send-email-dengcheng.zhu@gmail.com> <1290072458.18450.1.camel@e102144-lin.cambridge.arm.com> |
| Sender: | linux-mips-bounce@linux-mips.org |
Thanks. The commit you pointed out was also in this patch set (#3). But I think the return value should stick to 0, not 1. Something out of my consideration? Deng-Cheng 2010/11/18 Will Deacon <will.deacon@arm.com>: > On Thu, 2010-11-18 at 06:56 +0000, Deng-Cheng Zhu wrote: >> Leverage the commit for ARM by Will Deacon: >> >> 446a5a8b1eb91a6990e5c8fe29f14e7a95b69132 >> ARM: 6205/1: perf: ensure counter delta is treated as unsigned >> >> Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> >> --- >> arch/mips/kernel/perf_event.c | 2 +- >> 1 files changed, 1 insertions(+), 1 deletions(-) >> >> diff --git a/arch/mips/kernel/perf_event.c b/arch/mips/kernel/perf_event.c >> index 345232a..0f1cdf5 100644 >> --- a/arch/mips/kernel/perf_event.c >> +++ b/arch/mips/kernel/perf_event.c >> @@ -169,7 +169,7 @@ static void mipspmu_event_update(struct perf_event >> *event, >> unsigned long flags; >> int shift = 64 - TOTAL_BITS; >> s64 prev_raw_count, new_raw_count; >> - s64 delta; >> + u64 delta; >> >> again: >> prev_raw_count = local64_read(&hwc->prev_count); >> -- >> 1.7.1 > > Acked-by: Will Deacon <will.deacon@arm.com> > > You might also want to look at commit 65b4711f if you based > the MIPS port on the old ARM code. > > Thanks, > > Will > > -- > IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you. > > -- IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you. > > |
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