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Re: Question about Context register in TLB refilling

To: Ralf Baechle <ralf@linux-mips.org>
Subject: Re: Question about Context register in TLB refilling
From: "Maciej W. Rozycki" <macro@linux-mips.org>
Date: Sun, 24 Oct 2010 06:26:11 +0100 (BST)
Cc: Kevin Cernekee <cernekee@gmail.com>, "wilbur.chan" <wilbur512@gmail.com>, Linux MIPS Mailing List <linux-mips@linux-mips.org>
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On Mon, 18 Oct 2010, Ralf Baechle wrote:

> The design of the R4000 c0_context / c0_xcontext register assumes 8 byte
> ptes and a flat page table array.

 As I say you can increase the size by left-shifting the register.  
That's still cheaper than left-shifting and adding a 32-bit of worse yet a 
64-bit base.  Of course that implies higher yet an alignment and the PTE 
size of a power of two (which assuming at least a minimal level of sanity 
you want anyway).

 A flat structure is quite limiting (read: memory-greedy) indeed, but it 
looks to me with clever masking and shifting you should be able to get 
two-level page tables quite cheaply and easily too (on 32-bit).  Hmm...

> You can map the pagetables into virtual memory to get that and in fact 
> very old Linux/MIPS versions did that but that approach may result in 
> aliases on some processors so I eventually dropped it.  The 
> implementation requires nested TLB refill implementations and 
> (Linux/MIPS was still using a.out in this days) I implemented a new 
> relocation type to squeeze a cycle out of the slow path.

 Nested refills shouldn't be too much of a problem, but cache aliases 
always ask for troubles, hmm...  It may be worth investigating on 
processors with no aliases first, if at all.

  Maciej

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