| To: | Kevin Cernekee <cernekee@gmail.com> |
|---|---|
| Subject: | Re: [PATCH v2 8/9] MIPS: Honor L2 bypass bit |
| From: | "Maciej W. Rozycki" <macro@linux-mips.org> |
| Date: | Sun, 24 Oct 2010 03:40:15 +0100 (BST) |
| Cc: | Ralf Baechle <ralf@linux-mips.org>, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org |
| In-reply-to: | <AANLkTinJ4wU30AaBhcvJRLZ_iw-eo9tEkds8QA1S=Nqw@mail.gmail.com> |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <74b5d3ba9506b2e6d885546bd6dcdaec@localhost> <20101021125809.GA15031@linux-mips.org> <AANLkTinJ4wU30AaBhcvJRLZ_iw-eo9tEkds8QA1S=Nqw@mail.gmail.com> |
| Sender: | linux-mips-bounce@linux-mips.org |
| User-agent: | Alpine 2.00 (LFD 1167 2008-08-23) |
On Thu, 21 Oct 2010, Kevin Cernekee wrote: > FWIW, I did check the software user's manual for each of the four > processors in the list and verified that L2B is at CONFIG2 bit 12. It > would be very rude for an L2 designer to redefine those bits in > defiance of the SUM, no? To err is human -- people do all kinds of weird stuff, not necessarily on purpose. I think it should be safe to assume the bit is used properly until proved otherwise. > I also rechecked 24KE just now, and found that L2B is defined in the > latest rev of the SUM, but in my local copy (Revision 01.02) bit 12 is > the MSB of SS instead. Hmmm. Clearly a documentation bug -- notice how the width of the field disagress with the bit indices quoted. Maciej |
| <Prev in Thread] | Current Thread | [Next in Thread> |
|---|---|---|
| ||
| Previous by Date: | Re: [RFC 2/2] ftrace/MIPS: Add support for C version of recordmcount, wu zhangjin |
|---|---|
| Next by Date: | Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Maciej W. Rozycki |
| Previous by Thread: | Re: [PATCH v2 8/9] MIPS: Honor L2 bypass bit, Kevin Cernekee |
| Next by Thread: | [PATCH v2 22/22] bitops: remove minix bitops from asm/bitops.h, Akinobu Mita |
| Indexes: | [Date] [Thread] [Top] [All Lists] |