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Re: [PATCH resend 5/9] MIPS: sync after cacheflush

To: "Maciej W. Rozycki" <macro@linux-mips.org>
Subject: Re: [PATCH resend 5/9] MIPS: sync after cacheflush
From: "Gleb O. Raiko" <raiko@niisi.msk.ru>
Date: Thu, 21 Oct 2010 12:52:15 +0400
Cc: Ralf Baechle <ralf@linux-mips.org>, Kevin Cernekee <cernekee@gmail.com>, Shinya Kuribayashi <skuribay@pobox.com>, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org
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On 20.10.2010 21:26, Maciej W. Rozycki wrote:
On Wed, 20 Oct 2010, Gleb O. Raiko wrote:
  I'm not sure what you mean: whether the processor will snoop the value to
read in the store buffer or will it stall until the buffer has drained and
issue the load on the external bus?
I meant the latter.

  I can't see the behaviour of uncached loads wrt uncached stores clearly
documented anywhere for the R4400 processor (DEC used the SC variation,
BTW).  There's no mention of uncached loads to have SYNC properties.
I agree the docs are unclear here. They contain an example of cached and uncached stores (Ralf has pointed to already), but no clear explanation for mix of loads and stores. Sure, it's safer to keep both sync and uncached load.

Therefore in the context of one or more pending uncached stores I can
assume one of the three for an uncached load:

1. If the addresses match, then the value loaded is snooped in (retrieved
    from) the store buffer, no external cycle on the bus is seen.  This is
    what the R2020 WB did.

2. The load bypasses the stores and therefore reaches the external bus
    before the stores.  This is what the R3220 MB did and I believe the
    R2020 WB defaulted to in the case of no address match.

3. The load stalls until the outstanding stores have completed and only
    then appears on the external bus.

There's no hurt from using SYNC here and its semantics make it clear it
enforces the case #3 above even if not otherwise guaranteed.  Otherwise I
think the case #2 would be a reasonable default (i.e. one I'd recommend to
a processor designer) as draining the store buffer on any uncached load
whether needed or not is a waste of performance.
There is no such thing like performance in case of uncached loads.
The case #2 requires:
1. sync
2. additional operations (usually just a read) to pull data behind input buffers on an IO bus.

While it's ok to put that in MMIO reads/writes as you've done, it's almost impossible to program X server in that way, for example. This beast considers a frame buffer as an memory array with strong ordering. That's why I'd vote for the case #3. Not because it outperforms #2 in the real life (who cares for 0.0001% gain), but because IO devices requires strong ordering.

Gleb.

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