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[PATCH v2 8/9] MIPS: Honor L2 bypass bit

To: Ralf Baechle <ralf@linux-mips.org>
Subject: [PATCH v2 8/9] MIPS: Honor L2 bypass bit
From: Kevin Cernekee <cernekee@gmail.com>
Date: Wed, 20 Oct 2010 20:05:42 -0700
Cc: <linux-mips@linux-mips.org>, <linux-kernel@vger.kernel.org>
Original-recipient: rfc822;linux-mips@linux-mips.org
Sender: linux-mips-bounce@linux-mips.org
User-agent: vim 7.2
On many of the newer MIPS32 cores, CP0 CONFIG2 bit 12 (L2B) indicates
that the L2 cache is disabled and therefore Linux should not attempt
to use it.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
---
 arch/mips/mm/sc-mips.c |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index 5ab5fa8..f2e2886 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -79,6 +79,17 @@ static inline int __init mips_sc_probe(void)
                return 0;
 
        config2 = read_c0_config2();
+
+       /* Check the bypass bit (L2B) */
+       switch (c->cputype) {
+       case CPU_34K:
+       case CPU_74K:
+       case CPU_1004K:
+       case CPU_BMIPS5000:
+               if (config2 & (1 << 12))
+                       return 0;
+       }
+
        tmp = (config2 >> 4) & 0x0f;
        if (0 < tmp && tmp <= 7)
                c->scache.linesz = 2 << tmp;
-- 
1.7.0.4


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