|To:||"Maciej W. Rozycki" <email@example.com>|
|Subject:||Re: [PATCH resend 5/9] MIPS: sync after cacheflush|
|From:||"Gleb O. Raiko" <firstname.lastname@example.org>|
|Date:||Wed, 20 Oct 2010 12:05:42 +0400|
|Cc:||Ralf Baechle <email@example.com>, Kevin Cernekee <firstname.lastname@example.org>, Shinya Kuribayashi <email@example.com>, firstname.lastname@example.org, email@example.com|
|References:||<17ebecce124618ddf83ec6fe8e526f93@localhost> <17d8d27a2356640a4359f1a7dcbb3b42@localhost> <4CBC4F4E.firstname.lastname@example.org> <AANLkTinpry=XG-ZDgXJK-VB6QkBL2TO4-vrsV5Tc1eEs@mail.gmail.com> <alpine.LFD.email@example.com> <20101019123441.GJ27377@linux-mips.org> <alpine.LFD.firstname.lastname@example.org>|
|User-agent:||Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:126.96.36.199) Gecko/20091204 Thunderbird/3.0|
On 20.10.2010 0:11, Maciej W. Rozycki wrote:
That said, R4k DECstations seem to perform aggressive write buffering in the chipset and to make sure a write has propagated to an MMIO register a SYNC and an uncached read operation are necessary.
Just uncached read may be enough. R4k shall pull data from its store buffer on uncached read.
I haven't investigated DMA dependencies and I think we currently only have one TURBOchannel device/driver only (that is the DEFTA/defxx FDDI thingy) making use of the generic DMA API on DECstations. It seemed to work correctly the last time I tried; presumably either because the API Does The Right Thing, or by pure luck and right timings.
dfx_writel issues sync after store. BTW, it seems no uncached read issued here (just mb() is used, which seems to do sync only), so either those uncached read is not needed (unlikely) or data from dfx_writel wait somewhere in the chipset for being pulled by subsequent reads or writes.
|<Prev in Thread]||Current Thread||[Next in Thread>|
|Previous by Date:||Re: [PATCH 3/9] MIPS: Add BMIPS CP0 register definitions, Ralf Baechle|
|Next by Date:||Re: recent SIGBUS/SIGSEGV mips kernel bug, David Daney|
|Previous by Thread:||Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Maciej W. Rozycki|
|Next by Thread:||Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Maciej W. Rozycki|
|Indexes:||[Date] [Thread] [Top] [All Lists]|