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Re: [PATCH resend 5/9] MIPS: sync after cacheflush

To: "Maciej W. Rozycki" <macro@linux-mips.org>
Subject: Re: [PATCH resend 5/9] MIPS: sync after cacheflush
From: Ralf Baechle <ralf@linux-mips.org>
Date: Tue, 19 Oct 2010 13:34:41 +0100
Cc: Kevin Cernekee <cernekee@gmail.com>, Shinya Kuribayashi <skuribay@pobox.com>, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org
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On Tue, Oct 19, 2010 at 01:57:43AM +0100, Maciej W. Rozycki wrote:

>  Ah, the old issue of the write-back barrier.  I can't comment on 
> Loongson, but for DEC IIRC the write-back buffer only needs to be taken 
> care of for uncached writes and they take a path separate to cached 
> writes.  I'd have to dig out the details to be sure.  IIRC the most 
> pathological case was the R2020 WB chip, but that was only used on systems 
> that didn't do DMA (namely DECstatation 3100 and 2100 boxes).

See R4000 User's Manual Version 2, page 326, "Uncached Loads and Stores".
Of course this can only happen on cache coherent or multiprocessor systems.
I guess none of the supported DEC MIPS systems is affected.

  Ralf

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