|To:||Ralf Baechle <email@example.com>|
|Subject:||Re: [PATCH resend 5/9] MIPS: sync after cacheflush|
|From:||"Gleb O. Raiko" <firstname.lastname@example.org>|
|Date:||Tue, 19 Oct 2010 14:15:57 +0400|
|Cc:||Kevin Cernekee <email@example.com>, Shinya Kuribayashi <firstname.lastname@example.org>, email@example.com, firstname.lastname@example.org, email@example.com|
|References:||<17ebecce124618ddf83ec6fe8e526f93@localhost> <17d8d27a2356640a4359f1a7dcbb3b42@localhost> <4CBC4F4E.firstname.lastname@example.org> <20101018191936.GH27377@linux-mips.org> <AANLkTimmatKpOFATCPDxthN-9pZzzXRAOnLGR1_348email@example.com> <4CBD5CC9.firstname.lastname@example.org> <20101019091729.GA31405@linux-mips.org>|
|User-agent:||Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:220.127.116.11) Gecko/20091204 Thunderbird/3.0|
On 19.10.2010 13:17, Ralf Baechle wrote:
On Tue, Oct 19, 2010 at 12:54:33PM +0400, Gleb O. Raiko wrote: The MIPS32 BIS v2.6 spec says on page 92: "The CACHE instruction and the memory transactions which are sourced by the CACHE instruction, such as cache refill or cache writeback, obey the ordering and completion rules of the SYNC instruction." That's not as clearly spelt out as one would like but it seems to imply that only reads/writes preceeding the CACHE instruction are guaranteed to have completed that is the last CACHE instruction that was executed may still be incomplete.
I meant another piece:"For implementations which implement multiple level of caches ... <speaking about inclusive caches here> ... The software must place a SYNC instruction after the CACHE instruction whenever there are possible writebacks from the inner cache to ensure that the writeback data is resident in the outer cache before operating on the outer cache. ... <the rest of statement is a bogeyman story about not doing so>
For implementations which implement muliple level of caches without the inclusion property, the use of a SYNC instruction after the CACHE instruction is still needed whenever writeback data has to be resident in the next level of memory hierarchy."
It seems the last sentence shall be also applied for inclusive caches too. Gleb.
|<Prev in Thread]||Current Thread||[Next in Thread>|
|Previous by Date:||Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Ralf Baechle|
|Next by Date:||Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Ralf Baechle|
|Previous by Thread:||Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Ralf Baechle|
|Next by Thread:||[PATCH resend 6/9] MIPS: pfn_valid() is broken on low memory HIGHMEM systems, Kevin Cernekee|
|Indexes:||[Date] [Thread] [Top] [All Lists]|