Re: [PATCH resend 5/9] MIPS: sync after cacheflush

To:	Ralf Baechle <ralf@linux-mips.org>
Subject:	Re: [PATCH resend 5/9] MIPS: sync after cacheflush
From:	"Maciej W. Rozycki" <macro@linux-mips.org>
Date:	Tue, 19 Oct 2010 01:45:05 +0100 (BST)
Cc:	Kevin Cernekee <cernekee@gmail.com>, Shinya Kuribayashi <skuribay@pobox.com>, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org
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On Mon, 18 Oct 2010, Ralf Baechle wrote:

> I agree with you but I seem to remember having read something that suggests
> otherwise.  Oh well, maybe it's just something in the Cambridge water
> that makes my halocinate ;)

 Oh, come on!  Our water is reportedly among the best in the country.  If 
anyone is hallucinating, it must be everyone else! ;)

  Maciej

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Re: [PATCH resend 5/9] MIPS: sync after cacheflush, (continued) Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Maciej W. Rozycki Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Ralf Baechle Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Maciej W. Rozycki Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Gleb O. Raiko Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Maciej W. Rozycki Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Gleb O. Raiko Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Maciej W. Rozycki Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Ralf Baechle Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Kevin Cernekee Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Ralf Baechle Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Maciej W. Rozycki <= Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Gleb O. Raiko Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Ralf Baechle Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Gleb O. Raiko [PATCH resend 6/9] MIPS: pfn_valid() is broken on low memory HIGHMEM systems, Kevin Cernekee [PATCH v2 resend 7/9] MIPS: Move FIXADDR_TOP into spaces.h, Kevin Cernekee [PATCH resend 8/9] MIPS: Honor L2 bypass bit, Kevin Cernekee Re: [PATCH resend 8/9] MIPS: Honor L2 bypass bit, Ralf Baechle [PATCH resend 9/9] MIPS: Allow UserLocal on MIPS_R1 processors, Kevin Cernekee Re: [PATCH resend 9/9] MIPS: Allow UserLocal on MIPS_R1 processors, Ralf Baechle Re: [PATCH 1/9] MIPS: Decouple BMIPS CPU support from bcm47xx/bcm63xx SoC code, Florian Fainelli

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