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Re: Question about Context register in TLB refilling

To: Ralf Baechle <ralf@linux-mips.org>
Subject: Re: Question about Context register in TLB refilling
From: "Gleb O. Raiko" <raiko@niisi.msk.ru>
Date: Mon, 18 Oct 2010 18:03:51 +0400
Cc: "Maciej W. Rozycki" <macro@linux-mips.org>, Kevin Cernekee <cernekee@gmail.com>, "wilbur.chan" <wilbur512@gmail.com>, Linux MIPS Mailing List <linux-mips@linux-mips.org>
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On 18.10.2010 16:48, Ralf Baechle wrote:
On Mon, Oct 18, 2010 at 02:46:02PM +0400, Gleb O. Raiko wrote:
64 context on R2000/R3000, 256 on everything else but R6000 and RM9000
series, 4096 contexts on RM9000 and that context caching is already
there.  It's fairly lightweight except in the rare case where the
PID / ASID number overflows and a full TLB flush becomes necessary.  A
mm context switch only needs to reload the one wired TLB entry that maps
the pagetables so that's not too bad.

Ralf,

I counted from the opposite side. Size of KSEG2+KSEG3 is 1 GB, flat page table shall be 8 MB aligned to be stored in cp0 context, so we end up with 128 page tables in the theory (we have to reserve some space for other business too in practice).

If we are going to use a "standard" approach when only current page table is mapped, we know the address at compile time and don't need cp0 context at all. We can even has as many page tables as number of ASIDs for cpus with multiple page sizes but cp0 context is still out of play anyway.

Gleb.

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