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Re: Question about Context register in TLB refilling

To: "Gleb O. Raiko" <raiko@niisi.msk.ru>
Subject: Re: Question about Context register in TLB refilling
From: Ralf Baechle <ralf@linux-mips.org>
Date: Mon, 18 Oct 2010 13:48:38 +0100
Cc: "Maciej W. Rozycki" <macro@linux-mips.org>, Kevin Cernekee <cernekee@gmail.com>, "wilbur.chan" <wilbur512@gmail.com>, Linux MIPS Mailing List <linux-mips@linux-mips.org>
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On Mon, Oct 18, 2010 at 02:46:02PM +0400, Gleb O. Raiko wrote:

> On 18.10.2010 4:00, Ralf Baechle wrote:
> >The aliasing problem is solvable and it may be worth to revisit that old
> >piece of code again now 15 years later.
> 
> Before anybody will start to prepare patches, I'd like to note using
> c0_context allows less than 128 processes (their mm contexts in fact
> but who cares) to be directly mapped on 32-bit cpus. So, some kind
> of caching needs to be implemented and it will add overhead on every
> mm switch. Sure, this overhead might be bounded for a real case
> where there is a small number of processes, so they all fit in the
> cache.
> --- Beware, wild assumptions here ---
> I'm afraid the cost of such caching still will be higher than
> loading pgd_current even from main memory on tlb refill.
> --- End of wild assumptions ---

64 context on R2000/R3000, 256 on everything else but R6000 and RM9000
series, 4096 contexts on RM9000 and that context caching is already
there.  It's fairly lightweight except in the rare case where the
PID / ASID number overflows and a full TLB flush becomes necessary.  A
mm context switch only needs to reload the one wired TLB entry that maps
the pagetables so that's not too bad.  The ugly part are the nested
TLB exceptions.  I dumped that very early on when I realized the cache
alias issues my implementation had so the earliest usable kernel versions
had the tree walking reload handlers.  That's why I don't have any
benchmark results.

  Ralf

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