On Sun, Oct 17, 2010 at 08:33:24PM +0100, Maciej W. Rozycki wrote:
> > > 1) In linux ,esspecially in TLB refilling, is Context[PTEBase] used
> > > to store cpuid? (refer to build_get_pgde32 in tlbex.c)
> > On 32-bit systems, PTEBase stores a byte offset that can be added to
> > &pgd_current. i.e. smp_processor_id() * sizeof(unsigned long)
> > So the TLB refill handler can find pgd for the current CPU using code
> > that looks something like this:
> > 0: 401b2000 mfc0 k1,c0_context
> > 4: 3c1a8054 lui k0,0x8054
> > 8: 001bddc2 srl k1,k1,0x17
> > c: 035bd821 addu k1,k0,k1
> > ...
> > 14: 8f7b5008 lw k1,20488(k1)
> > where pgd_current is at 0x8054_5008, and PTEBase is 0, 4, 8, 12, ...
> It has been always making me wonder (though not as much to go and dig
> through our code ;) ) why Linux is uncapable of using the value presented
> by the CPU in the CP0 Context register as is, or perhaps after a trivial
> operation such as a left-shift by a constant number of bits (where the
> size of the page entry slot assumed by hardware turned out too small).
> There should be no need to add another constant as in the piece of code
> you have quoted -- this constant should already have been preloaded to
> this register when switching the context the last time. The design of the
> TLB refill exception in the MIPS Architecture has been such as to allow
> this register to be readily used as an address into the page table.
The design of the R4000 c0_context / c0_xcontext register assumes 8 byte
ptes and a flat page table array. You can map the pagetables into virtual
memory to get that and in fact very old Linux/MIPS versions did that but
that approach may result in aliases on some processors so I eventually
dropped it. The implementation requires nested TLB refill implementations
and (Linux/MIPS was still using a.out in this days) I implemented a new
relocation type to squeeze a cycle out of the slow path.
The aliasing problem is solvable and it may be worth to revisit that old
piece of code again now 15 years later.