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Re: Question about Context register in TLB refilling

To: Kevin Cernekee <cernekee@gmail.com>
Subject: Re: Question about Context register in TLB refilling
From: "Maciej W. Rozycki" <macro@linux-mips.org>
Date: Sun, 17 Oct 2010 22:56:31 +0100 (BST)
Cc: "wilbur.chan" <wilbur512@gmail.com>, Linux MIPS Mailing List <linux-mips@linux-mips.org>
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On Sun, 17 Oct 2010, Kevin Cernekee wrote:

> On plain old 32-bit MIPS:
> 
> The pgd entry for "va" is at address: (unsigned long)pgd + ((va >> 22) << 2)
> 
> i.e. each 4-byte entry in the pgd table represents 4MB of virtual address 
> space.
> 
> PTEBase only gives you 9 bits to work with.  If you use it to store
> pgd[31:23] directly, that means every pgd needs to be 8MB-aligned -
> ouch.

 Good point!  I believe the original idea behind the Context and XContext 
registers was to put page tables somewhere within KSEG2/3 or XKSSEG which 
would make this alignment restriction not a problem, but I realise the 
overhead of placing page tables in paged memory may be higher than that of 
our current arrangement.

 I wonder however if such performance evaluation was actually ever made or 
whether it was the complexity of having page tables paged alone that 
scared people off. ;)

  Maciej

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