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Re: [PATCH 1/9] MIPS: Decouple BMIPS CPU support from bcm47xx/bcm63xx So

To: Kevin Cernekee <cernekee@gmail.com>
Subject: Re: [PATCH 1/9] MIPS: Decouple BMIPS CPU support from bcm47xx/bcm63xx SoC code
From: Florian Fainelli <ffainelli@freebox.fr>
Date: Sun, 17 Oct 2010 18:59:43 +0200
Cc: Ralf Baechle <ralf@linux-mips.org>, mbizon@freebox.fr, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org
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Hello Kevin,

Le Saturday 16 October 2010 23:22:30, Kevin Cernekee a écrit :
> BMIPS processor cores are used in 50+ different chipsets spread across
> 5+ product lines.  In many cases the chipsets do not share the same
> peripheral register layouts, the same register blocks, the same
> interrupt controllers, the same memory maps, or much of anything else.
> 
> But, across radically different SoCs that share nothing more than the
> same BMIPS CPU, a few things are still mostly constant:
> 
> SMP operations
> Access to performance counters
> DMA cache coherency quirks
> Cache and memory bus configuration
> 
> So, it makes sense to treat each BMIPS processor type as a generic
> "building block," rather than tying it to a specific SoC.  This makes it
> easier to support a large number of BMIPS-based chipsets without
> unnecessary duplication of code, and provides the infrastructure needed
> to support BMIPS-proprietary features.
> 
> Signed-off-by: Kevin Cernekee <cernekee@gmail.com>

I boot tested all of your nine patches on a BCM6348 system without problems.

Tested-by: Florian Fainelli <ffainelli@freebox.fr>
--
Florian

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