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[PATCH resend 8/9] MIPS: Honor L2 bypass bit

To: Ralf Baechle <ralf@linux-mips.org>
Subject: [PATCH resend 8/9] MIPS: Honor L2 bypass bit
From: Kevin Cernekee <cernekee@gmail.com>
Date: Sat, 16 Oct 2010 14:22:37 -0700
Cc: <linux-mips@linux-mips.org>, <linux-kernel@vger.kernel.org>
In-reply-to: <17ebecce124618ddf83ec6fe8e526f93@localhost>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <17ebecce124618ddf83ec6fe8e526f93@localhost>
Sender: linux-mips-bounce@linux-mips.org
User-agent: vim 7.2
If CP0 CONFIG2 bit 12 (L2B) is set, the L2 cache is disabled and
therefore Linux should not attempt to use it.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
---
 arch/mips/mm/sc-mips.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index 5ab5fa8..d072b25 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -79,6 +79,11 @@ static inline int __init mips_sc_probe(void)
                return 0;
 
        config2 = read_c0_config2();
+
+       /* bypass bit */
+       if (config2 & (1 << 12))
+               return 0;
+
        tmp = (config2 >> 4) & 0x0f;
        if (0 < tmp && tmp <= 7)
                c->scache.linesz = 2 << tmp;
-- 
1.7.0.4


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