| To: | David Daney <ddaney@caviumnetworks.com> |
|---|---|
| Subject: | Re: [PATCH 03/14] MIPS: Octeon: Update L2 Cache code for CN63XX |
| From: | Ralf Baechle <ralf@linux-mips.org> |
| Date: | Mon, 11 Oct 2010 13:54:14 +0100 |
| Cc: | linux-mips@linux-mips.org |
| In-reply-to: | <1286492633-26885-4-git-send-email-ddaney@caviumnetworks.com> |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <1286492633-26885-1-git-send-email-ddaney@caviumnetworks.com> <1286492633-26885-4-git-send-email-ddaney@caviumnetworks.com> |
| Sender: | linux-mips-bounce@linux-mips.org |
| User-agent: | Mutt/1.5.21 (2010-09-15) |
On Thu, Oct 07, 2010 at 04:03:42PM -0700, David Daney wrote: > The CN63XX has a different L2 cache architecture. Update the helper > functions to reflect this. > > Some joining of split lines was also done to improve readability, as > well as reformatting of comments. I fixed the trailing blank line the patch added to arch/mips/cavium-octeon/executive/cvmx-l2c.c and queued it for 2.6.37. Thanks! Ralf |
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