| To: | linux-mips@linux-mips.org, ralf@linux-mips.org |
|---|---|
| Subject: | [PATCH 04/14] MIPS: Add identifiers for Octeon II CPUs. |
| From: | David Daney <ddaney@caviumnetworks.com> |
| Date: | Thu, 7 Oct 2010 16:03:43 -0700 |
| Cc: | David Daney <ddaney@caviumnetworks.com> |
| In-reply-to: | <1286492633-26885-1-git-send-email-ddaney@caviumnetworks.com> |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <1286492633-26885-1-git-send-email-ddaney@caviumnetworks.com> |
| Sender: | linux-mips-bounce@linux-mips.org |
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
arch/mips/include/asm/cpu.h | 3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index b201a8f..049a189 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -131,6 +131,7 @@
#define PRID_IMP_CAVIUM_CN56XX 0x0400
#define PRID_IMP_CAVIUM_CN50XX 0x0600
#define PRID_IMP_CAVIUM_CN52XX 0x0700
+#define PRID_IMP_CAVIUM_CN63XX 0x9000
/*
* These are the PRID's for when 23:16 == PRID_COMP_INGENIC
@@ -231,7 +232,7 @@ enum cpu_type_enum {
* MIPS64 class processors
*/
CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
- CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,
+ CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2,
CPU_LAST
};
--
1.7.2.3
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