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Re: How is interrupt handling on MIPS SMP?

To: wu zhangjin <>
Subject: Re: How is interrupt handling on MIPS SMP?
From: Adam Jiang <>
Date: Sun, 29 Aug 2010 15:57:40 +0900
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> Hi, Adam
> On 8/28/10, Adam Jiang <> wrote:
> > How dose interrupt be handled on SMP build on MIPS architecture? Does
> > mips-linux support SMP?
> >
> $ grep SYS_SUPPORTS_SMP -ur arch/mips/Kconfig | egrep -v "config|depend" | wc 
> -l
> 6
> You can get more information from the book "See MIPS Run Linux" version 2.

Thank you, Wu. I'd like to read the book ASAP.

I have gotten a general image how multi-APIC system distribute IRQs to
each CPU on x86 architecture. For misp, is there a mechanism to do the
same thing?

Another question is about the comments in file


it is said "8 interrupt sources" things could not be applied to SMP.
What dose this mean? How is MIPS CPU interrupts handled? Could I get a
general information from MIPS programmer manual?

Best regards,

> Regards,
> Wu Zhangjin

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