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[PATCH 1/3] MIPS: Loongson: Remove set_irq_trigger_mode()

To: Ralf Baechle <ralf@linux-mips.org>
Subject: [PATCH 1/3] MIPS: Loongson: Remove set_irq_trigger_mode()
From: Wu Zhangjin <wuzhangjin@gmail.com>
Date: Sat, 24 Jul 2010 09:22:13 +0800
Cc: linux-mips@linux-mips.org, Wu Zhangjin <wuzhangjin@gmail.com>
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In-reply-to: <cover.1279934355.git.wuzhangjin@gmail.com>
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References: <cover.1279934355.git.wuzhangjin@gmail.com>
Sender: linux-mips-bounce@linux-mips.org
From: Wu Zhangjin <wuzhangjin@gmail.com>

set_irq_trigger_mode() is not needed by all of the platforms, remove it
and put the related source code into mach_init_irq().

This will let gdium share the common irq.c without adding an empty
set_irq_trigger_mode().

Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
---
 arch/mips/include/asm/mach-loongson/loongson.h |    1 -
 arch/mips/loongson/common/irq.c                |    3 ---
 arch/mips/loongson/fuloong-2e/irq.c            |   11 ++++-------
 arch/mips/loongson/lemote-2f/irq.c             |   11 ++++-------
 4 files changed, 8 insertions(+), 18 deletions(-)

diff --git a/arch/mips/include/asm/mach-loongson/loongson.h 
b/arch/mips/include/asm/mach-loongson/loongson.h
index 8b10cfc..ef81d9c 100644
--- a/arch/mips/include/asm/mach-loongson/loongson.h
+++ b/arch/mips/include/asm/mach-loongson/loongson.h
@@ -51,7 +51,6 @@ extern char loongson_cmdline[COMMAND_LINE_SIZE];
 /* irq operation functions */
 extern void bonito_irqdispatch(void);
 extern void __init bonito_irq_init(void);
-extern void __init set_irq_trigger_mode(void);
 extern void __init mach_init_irq(void);
 extern void mach_irq_dispatch(unsigned int pending);
 extern int mach_i8259_irq(void);
diff --git a/arch/mips/loongson/common/irq.c b/arch/mips/loongson/common/irq.c
index 20e7328..987feeb 100644
--- a/arch/mips/loongson/common/irq.c
+++ b/arch/mips/loongson/common/irq.c
@@ -56,9 +56,6 @@ void __init arch_init_irq(void)
         */
        clear_c0_status(ST0_IM | ST0_BEV);
 
-       /* setting irq trigger mode */
-       set_irq_trigger_mode();
-
        /* no steer */
        LOONGSON_INTSTEER = 0;
 
diff --git a/arch/mips/loongson/fuloong-2e/irq.c 
b/arch/mips/loongson/fuloong-2e/irq.c
index 320e937..99e08c3 100644
--- a/arch/mips/loongson/fuloong-2e/irq.c
+++ b/arch/mips/loongson/fuloong-2e/irq.c
@@ -44,13 +44,6 @@ static struct irqaction cascade_irqaction = {
        .name = "cascade",
 };
 
-void __init set_irq_trigger_mode(void)
-{
-       /* most bonito irq should be level triggered */
-       LOONGSON_INTEDGE = LOONGSON_ICU_SYSTEMERR | LOONGSON_ICU_MASTERERR |
-           LOONGSON_ICU_RETRYERR | LOONGSON_ICU_MBOXES;
-}
-
 void __init mach_init_irq(void)
 {
        /* init all controller
@@ -59,6 +52,10 @@ void __init mach_init_irq(void)
         *   32-63        ------> bonito irq
         */
 
+       /* most bonito irq should be level triggered */
+       LOONGSON_INTEDGE = LOONGSON_ICU_SYSTEMERR | LOONGSON_ICU_MASTERERR |
+           LOONGSON_ICU_RETRYERR | LOONGSON_ICU_MBOXES;
+
        /* Sets the first-level interrupt dispatcher. */
        mips_cpu_irq_init();
        init_i8259_irqs();
diff --git a/arch/mips/loongson/lemote-2f/irq.c 
b/arch/mips/loongson/lemote-2f/irq.c
index 1d8b4d2..c6db7e7 100644
--- a/arch/mips/loongson/lemote-2f/irq.c
+++ b/arch/mips/loongson/lemote-2f/irq.c
@@ -91,13 +91,6 @@ void mach_irq_dispatch(unsigned int pending)
                spurious_interrupt();
 }
 
-void __init set_irq_trigger_mode(void)
-{
-       /* setup cs5536 as high level trigger */
-       LOONGSON_INTPOL = LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1;
-       LOONGSON_INTEDGE &= ~(LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1);
-}
-
 static irqreturn_t ip6_action(int cpl, void *dev_id)
 {
        return IRQ_HANDLED;
@@ -122,6 +115,10 @@ void __init mach_init_irq(void)
         *   32-63        ------> bonito irq
         */
 
+       /* setup cs5536 as high level trigger */
+       LOONGSON_INTPOL = LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1;
+       LOONGSON_INTEDGE &= ~(LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1);
+
        /* Sets the first-level interrupt dispatcher. */
        mips_cpu_irq_init();
        init_i8259_irqs();
-- 
1.7.0.4


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