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[PATCH 2/4] MIPS: EMMA2RH: Remove EMMA2RH_CPU_CASCADE

To: linux-mips@linux-mips.org
Subject: [PATCH 2/4] MIPS: EMMA2RH: Remove EMMA2RH_CPU_CASCADE
From: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com>
Date: Thu, 17 Jun 2010 20:36:13 +0900
In-reply-to: <4C1A0801.60405@renesas.com>
References: <4C1A0801.60405@renesas.com>
Sender: linux-mips-bounce@linux-mips.org
User-agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.1.9) Gecko/20100317 Lightning/1.0b1 Thunderbird/3.0.4
Although all EMMAxxx SoCs can support IP2 and IP3 hardware interrupts,
current EMMA2RH plat_irq_dispatch() supports IP2 only.  We can make it
configurable in the future, but for the time being, would like to make
things explicitly allcated to IP2 in accordance with plat_irq_dispatch().

Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com>
---
 arch/mips/emma/markeins/irq.c        |    2 +-
 arch/mips/include/asm/emma/emma2rh.h |    1 -
 2 files changed, 1 insertions(+), 2 deletions(-)

diff --git a/arch/mips/emma/markeins/irq.c b/arch/mips/emma/markeins/irq.c
index 1d1c806..3a96799 100644
--- a/arch/mips/emma/markeins/irq.c
+++ b/arch/mips/emma/markeins/irq.c
@@ -301,7 +301,7 @@ void __init arch_init_irq(void)
        /* setup cascade interrupts */
        setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE, &irq_cascade);
        setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_GPIO_CASCADE, &irq_cascade);
-       setup_irq(MIPS_CPU_IRQ_BASE + CPU_EMMA2RH_CASCADE, &irq_cascade);
+       setup_irq(MIPS_CPU_IRQ_BASE + 2, &irq_cascade);
 }
 
 asmlinkage void plat_irq_dispatch(void)
diff --git a/arch/mips/include/asm/emma/emma2rh.h 
b/arch/mips/include/asm/emma/emma2rh.h
index fcc0064..95d0b7e 100644
--- a/arch/mips/include/asm/emma/emma2rh.h
+++ b/arch/mips/include/asm/emma/emma2rh.h
@@ -101,7 +101,6 @@
 
 #define NUM_EMMA2RH_IRQ                96
 
-#define CPU_EMMA2RH_CASCADE    2
 #define EMMA2RH_IRQ_BASE       (MIPS_CPU_IRQ_BASE + 8)
 
 /*
-- 
1.7.1


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