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Re: [RFC][PATCH 01/26] MIPS: Add base support for Ingenic JZ4740 System-

To: Florian Fainelli <florian@openwrt.org>
Subject: Re: [RFC][PATCH 01/26] MIPS: Add base support for Ingenic JZ4740 System-on-a-Chip
From: Lars-Peter Clausen <lars@metafoo.de>
Date: Thu, 03 Jun 2010 19:03:03 +0200
Cc: Ralf Baechle <ralf@linux-mips.org>, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org
In-reply-to: <201006031627.31308.florian@openwrt.org>
References: <1275505397-16758-1-git-send-email-lars@metafoo.de> <1275505397-16758-2-git-send-email-lars@metafoo.de> <201006031627.31308.florian@openwrt.org>
Sender: linux-mips-bounce@linux-mips.org
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Hi Florian

Florian Fainelli wrote:
> Hi Lars,
>
> On Wednesday 02 June 2010 21:02:52 Lars-Peter Clausen wrote:
>   
>> This patch adds a new cpu type for the JZ4740 to the Linux MIPS
>> architecture code. It also adds the iomem addresses for the different
>> components found on a JZ4740 SoC.
>>
>> Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
>> ---
>>     
> [snip]
>
>   
>>       * MIPS64 class processors
>> diff --git a/arch/mips/include/asm/mach-jz4740/base.h
>> b/arch/mips/include/asm/mach-jz4740/base.h new file mode 100644
>> index 0000000..cba3aae
>> --- /dev/null
>> +++ b/arch/mips/include/asm/mach-jz4740/base.h
>> @@ -0,0 +1,28 @@
>> +#ifndef __ASM_MACH_JZ4740_BASE_H__
>> +#define __ASM_MACH_JZ4740_BASE_H__
>> +
>> +#define JZ4740_CPM_BASE_ADDR        0xb0000000
>> +#define JZ4740_INTC_BASE_ADDR       0xb0001000
>> +#define JZ4740_TCU_BASE_ADDR        0xb0002000
>> +#define JZ4740_WDT_BASE_ADDR        0xb0002000
>> +#define JZ4740_RTC_BASE_ADDR        0xb0003000
>> +#define JZ4740_GPIO_BASE_ADDR       0xb0010000
>> +#define JZ4740_AIC_BASE_ADDR        0xb0020000
>> +#define JZ4740_ICDC_BASE_ADDR       0xb0020000
>> +#define JZ4740_MSC_BASE_ADDR        0xb0021000
>> +#define JZ4740_UART0_BASE_ADDR      0xb0030000
>> +#define JZ4740_UART1_BASE_ADDR      0xb0031000
>> +#define JZ4740_I2C_BASE_ADDR        0xb0042000
>> +#define JZ4740_SSI_BASE_ADDR        0xb0043000
>> +#define JZ4740_SADC_BASE_ADDR       0xb0070000
>> +#define JZ4740_EMC_BASE_ADDR        0xb3010000
>> +#define JZ4740_DMAC_BASE_ADDR       0xb3020000
>> +#define JZ4740_UHC_BASE_ADDR        0xb3030000
>> +#define JZ4740_UDC_BASE_ADDR        0xb3040000
>> +#define JZ4740_LCD_BASE_ADDR        0xb3050000
>> +#define JZ4740_SLCD_BASE_ADDR       0xb3050000
>> +#define JZ4740_CIM_BASE_ADDR        0xb3060000
>> +#define JZ4740_IPU_BASE_ADDR        0xb3080000
>> +#define JZ4740_ETH_BASE_ADDR        0xb3100000
>>     
>
> Any reasons why you prefered virtual addresses here instead of physical ones?
> You might also want to define a "true" base address and compute the registers
> offset relatively to this base address for better clarity.
>
>   
This is historically grown and I agree that I should rather use the
physical addresses here, especially because they are only used together
with CPHYSADDR everywhere now.

Thanks for reviewing
- Lars

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