| To: | Deng-Cheng Zhu <dengcheng.zhu@gmail.com> |
|---|---|
| Subject: | Re: [PATCH v5 06/12] MIPS: add support for hardware performance events (mipsxx) |
| From: | David Daney <david.s.daney@gmail.com> |
| Date: | Sat, 29 May 2010 11:13:29 -0700 |
| Cc: | linux-mips@linux-mips.org, ralf@linux-mips.org, a.p.zijlstra@chello.nl, paulus@samba.org, mingo@elte.hu, acme@redhat.com, jamie.iles@picochip.com, will.deacon@arm.com |
| Dkim-signature: | v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:message-id:date:from :user-agent:mime-version:to:cc:subject:references:in-reply-to :content-type:content-transfer-encoding; bh=i9D7pQb7+IWK8Js47myxnX1xob36GZ87QAghBq61L/A=; b=F92JcVSbTN8u0wTPlYIWlIHbWdg0IW4MztbOsg5TvTUDuLPAI25GDQqelncqWbZ/gB ZMRJ6VknF2iAm8cRnzx4a/OXAJz+bjeR294A4U5TCKEdK+L0nRsxE3yx6OcJW4ORKRnK rD0aFBNsu6GLBy61ooykNn0Z2tztNaxL5Tlkg= |
| Domainkey-signature: | a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; b=i1KLNhQkWEEPiWhbYM2RMNAp9zihtZKn58dLtjBhTGhyj4ECHSIaBH4LzYfZHhcrnb BYeBaj2PmdtoOw/c5obKDKmJY5WpsXbm1Ku3uBqgvObAs3eoBSuK+LtAkpQCyBg9LeCI xV6xPcI9ui46gkKr355FKHCB8ZAVQfFYaO5J0= |
| In-reply-to: | <AANLkTim22Di_l7pM_qGA79MA0xejpi0Lo1OTZqCvP7-L@mail.gmail.com> |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <1274965420-5091-1-git-send-email-dengcheng.zhu@gmail.com> <1274965420-5091-7-git-send-email-dengcheng.zhu@gmail.com> <4BFEF5D7.4050502@gmail.com> <AANLkTim22Di_l7pM_qGA79MA0xejpi0Lo1OTZqCvP7-L@mail.gmail.com> |
| Sender: | linux-mips-bounce@linux-mips.org |
| User-agent: | Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.9) Gecko/20100430 Fedora/3.0.4-2.fc11 Thunderbird/3.0.4 |
On 05/28/2010 08:10 PM, Deng-Cheng Zhu wrote: 2010/5/28 David Daney<david.s.daney@gmail.com>:General comments: Can you separate the code that reads and writes the performance counter registers from the definitions of the various counters themselves?[DC]: 1) Do you mean to move M_PERFCTL_* stuff out into pmu.h (or mipsregs.h)? If yes, that's OK. Again (my reply for [1/12] mentions this for the 1st time): After making Oprofile use Perf-events as backend (patches 8~12 do this), register definitions and read/write functions will locate in pmu.h (or mipsregs.h) and perf_event_$cpu.c, respectively. 2) According to your reply to [7/12], do you mean the perf counter read/write functions (such as mipsxx_pmu_read_counter()) are generic support functions? No, they are specific for mipsxx CPUs. Basically what I had in mind is that for all MIPS CPUs that have this style of performance counters, the counters are all read in the same manner (by reading the c0_PerfCnt registers). However each CPU type has its own set of events that can be counted. So I was thinking to separate the common code that accesses the registers from the CPU specific code that deals with the specific names and properties of the various events. David Daney |
| Previous by Date: | Re: [PATCH] mips: drop CLEAN_FILES from arch/mips/Makefile, Wu Zhangjin |
|---|---|
| Next by Date: | Re: [PATCH v5 01/12] MIPS/Oprofile: extract PMU defines/helper functions for sharing, David Daney |
| Previous by Thread: | Re: [PATCH v5 06/12] MIPS: add support for hardware performance events (mipsxx), Deng-Cheng Zhu |
| Next by Thread: | [PATCH v5 07/12] MIPS/Perf-events: add raw event support for mipsxx 24K/34K/74K/1004K, Deng-Cheng Zhu |
| Indexes: | [Date] [Thread] [Top] [All Lists] |