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Re: [PATCH v5 04/12] MIPS: add support for hardware performance

To: David Daney <david.s.daney@gmail.com>
Subject: Re: [PATCH v5 04/12] MIPS: add support for hardware performance events (skeleton)
From: Deng-Cheng Zhu <dengcheng.zhu@gmail.com>
Date: Sat, 29 May 2010 11:08:41 +0800
Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, a.p.zijlstra@chello.nl, paulus@samba.org, mingo@elte.hu, acme@redhat.com, jamie.iles@picochip.com, will.deacon@arm.com
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2010/5/28 David Daney <david.s.daney@gmail.com>:
> This depends on not consistent with the #if conditions in [01/12] for pmu.h.
>  They should be I think.
[DC]: It's a subset. If the code passes the test on other CPUs (such as
CPU_SB1), we can add them here.


> Probably removing the tests from pmu.h and encoding them here is better.
[DC]: According to my comments for [1/12], how about keeping them untouched
for now?


> IANAL, but who holds the copyright?  You or MTI ?
[DC]: OK. Will change like this:
Copyright (C) 2010 MIPS Technologies, Inc.
Author: Deng-Cheng Zhu


> This shadows the declaration in asm/time.h.  Declare it in exactly one place
> please.
[DC]: OK.


> Same thing about the copyright.
[DC]: OK.


> Not quite true.  They use the high bit, that can be either 31 or 63
> depending on the width of the counters.
[DC]: OK. Will change to consider 64-bit counters.


> Counters can be 64-bits wide, unsigned int is only 32-bits wide.
[DC]: OK.


Deng-Cheng

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