| To: | Ralf Baechle <ralf@linux-mips.org> |
|---|---|
| Subject: | Re: [PATCH] Oprofile: Loongson: Fixup of irq handler |
| From: | Wu Zhangjin <wuzhangjin@gmail.com> |
| Date: | Sun, 09 May 2010 09:35:19 +0800 |
| Cc: | linux-mips@linux-mips.org |
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| In-reply-to: | <1273165186-29153-1-git-send-email-wuzhangjin@gmail.com> |
| Organization: | DSLab, Lanzhou University, China |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <1273165186-29153-1-git-send-email-wuzhangjin@gmail.com> |
| Reply-to: | wuzhangjin@gmail.com |
| Sender: | linux-mips-bounce@linux-mips.org |
Hi, Ralf
This one is urgent, could you please review it, thanks ;)
Regards,
Wu Zhangjin
On Fri, 2010-05-07 at 00:59 +0800, Wu Zhangjin wrote:
> The interrupt enable bit of performance counters of Loongson is in the
> control register($24), not in the counter register, so, in
> loongson2_perfcount_handler(), we need to use
>
> enabled = read_c0_perfctrl() & LOONGSON2_PERFCNT_INT_EN;
>
> instead of
>
> enabled = read_c0_perfcnt() & LOONGSON2_PERFCNT_INT_EN;
>
> Reported-by: Xu Hengyang <hengyang@mail.ustc.edu.cn>
> Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
> ---
> arch/mips/oprofile/op_model_loongson2.c | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/arch/mips/oprofile/op_model_loongson2.c
> b/arch/mips/oprofile/op_model_loongson2.c
> index 29e2326..fa3bf66 100644
> --- a/arch/mips/oprofile/op_model_loongson2.c
> +++ b/arch/mips/oprofile/op_model_loongson2.c
> @@ -122,7 +122,7 @@ static irqreturn_t loongson2_perfcount_handler(int irq,
> void *dev_id)
> */
>
> /* Check whether the irq belongs to me */
> - enabled = read_c0_perfcnt() & LOONGSON2_PERFCNT_INT_EN;
> + enabled = read_c0_perfctrl() & LOONGSON2_PERFCNT_INT_EN;
> if (!enabled)
> return IRQ_NONE;
> enabled = reg.cnt1_enabled | reg.cnt2_enabled;
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