[PATCH] MIPS: Coding style cleanups of access of FCSR rounding mode bits

[Shane McDonald <mcdonald.shane@gmail.com>]

This patch replaces references to the magic number 0x3 with
constants and macros indicating the real purpose of those bits.
They are the rounding mode bits of the FCSR register.

Signed-off-by: Shane McDonald <mcdonald.shane@gmail.com>
---
NOTE: This patch depends on the patch
"MIPS FPU emulator: allow Cause bits of FCSR to be writeable by ctc1"
having already been applied.

 arch/mips/math-emu/cp1emu.c |   11 ++++++-----
 1 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index f2338d1..47842b7 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -354,7 +354,8 @@ static int cop1Emulate(struct pt_regs *xcp, struct 
mips_fpu_struct *ctx)
 
                        if (MIPSInst_RD(ir) == FPCREG_CSR) {
                                value = ctx->fcr31;
-                               value = (value & ~0x3) | mips_rm[value & 0x3];
+                               value = (value & ~FPU_CSR_RM) |
+                                       mips_rm[modeindex(value)];
 #ifdef CSRTRACE
                                printk("%p gpr[%d]<-csr=%08x\n",
                                        (void *) (xcp->cp0_epc),
@@ -907,7 +908,7 @@ static int fpu_emu(struct pt_regs *xcp, struct 
mips_fpu_struct *ctx,
                        ieee754sp fs;
 
                        SPFROMREG(fs, MIPSInst_FS(ir));
-                       ieee754_csr.rm = ieee_rm[MIPSInst_FUNC(ir) & 0x3];
+                       ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
                        rv.w = ieee754sp_tint(fs);
                        ieee754_csr.rm = oldrm;
                        rfmt = w_fmt;
@@ -933,7 +934,7 @@ static int fpu_emu(struct pt_regs *xcp, struct 
mips_fpu_struct *ctx,
                        ieee754sp fs;
 
                        SPFROMREG(fs, MIPSInst_FS(ir));
-                       ieee754_csr.rm = ieee_rm[MIPSInst_FUNC(ir) & 0x3];
+                       ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
                        rv.l = ieee754sp_tlong(fs);
                        ieee754_csr.rm = oldrm;
                        rfmt = l_fmt;
@@ -1081,7 +1082,7 @@ static int fpu_emu(struct pt_regs *xcp, struct 
mips_fpu_struct *ctx,
                        ieee754dp fs;
 
                        DPFROMREG(fs, MIPSInst_FS(ir));
-                       ieee754_csr.rm = ieee_rm[MIPSInst_FUNC(ir) & 0x3];
+                       ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
                        rv.w = ieee754dp_tint(fs);
                        ieee754_csr.rm = oldrm;
                        rfmt = w_fmt;
@@ -1107,7 +1108,7 @@ static int fpu_emu(struct pt_regs *xcp, struct 
mips_fpu_struct *ctx,
                        ieee754dp fs;
 
                        DPFROMREG(fs, MIPSInst_FS(ir));
-                       ieee754_csr.rm = ieee_rm[MIPSInst_FUNC(ir) & 0x3];
+                       ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
                        rv.l = ieee754dp_tlong(fs);
                        ieee754_csr.rm = oldrm;
                        rfmt = l_fmt;
-- 
1.5.6.5