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[PATCH v3 0/4] MIPS performance event support v3

To: linux-mips@linux-mips.org, ralf@linux-mips.org
Subject: [PATCH v3 0/4] MIPS performance event support v3
From: Deng-Cheng Zhu <dengcheng.zhu@gmail.com>
Date: Wed, 5 May 2010 21:55:30 +0800
Cc: a.p.zijlstra@chello.nl, paulus@samba.org, mingo@elte.hu, acme@redhat.com, jamie.iles@picochip.com, Deng-Cheng Zhu <dengcheng.zhu@gmail.com>
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This patch series implemented the low-level logic for the Linux
performance counter subsystem on MIPS, which enables the collection of
all sorts of HW/SW performance events based on per-CPU or per-task. For
more information, please refer to tools/perf/Documentation/perf.txt.

Development tests were carried out on the Malta-R board. 24K/34K/74K/1004K
cores and SMVP/UP kernels have been basically tested.

CHANGES:
-----------------------------
v3 - v2:
- adding 1004K core support.
- slightly adjusting the code structure.
- adding more comments in the code.
- fixing some small coding style issues.
v2 - v1:
- Adjusting code structure as suggested by Wu Zhangjin. With this change,
hardware performance event support for loongson2 and rm9000 can be
conveniently implemented by adding and including new files like
perf_event_loongson2.c; Oprofile and Perf for MIPS are now sharing pmu.h;
Naming changes were made to some functions.
- Fixing the generic atomic64 issue reported by David Daney. Currently,
32bit kernel is using the generic version from lib. When Ralf Baechle's
common atomic64 version is ready, this may change.
- Adding raw event support. For more details, please refer to the code
comments for mipsxx_pmu_map_raw_event().
- Adding new software events - PERF_COUNT_SW_ALIGNMENT_FAULTS and
PERF_COUNT_SW_EMULATION_FAULTS.
- Fixing some small bugs.
- Adding new comments for the code.
- Making some code style changes.
v1:
- Using generic atomic64 operations from lib.
- SMVP/UP kernels are supported (not for SMTC).
- 24K/34K/74K cores are implemented.
- Currently working when Oprofile is _not_ available.
- Minimal software perf events are supported.
-----------------------------

Deng-Cheng Zhu (4):
  MIPS/Oprofile: extract PMU defines/helper functions for sharing
  MIPS: use generic atomic64 in non-64bit kernels
  MIPS: add support for software performance events
  MIPS: add support for hardware performance events

 arch/mips/Kconfig                       |   11 +
 arch/mips/include/asm/atomic.h          |    4 +
 arch/mips/include/asm/perf_event.h      |   28 +
 arch/mips/include/asm/pmu.h             |  244 +++++++++
 arch/mips/kernel/Makefile               |    2 +
 arch/mips/kernel/perf_event.c           |  604 +++++++++++++++++++++
 arch/mips/kernel/perf_event_mipsxx.c    |  869 +++++++++++++++++++++++++++++++
 arch/mips/kernel/traps.c                |   18 +-
 arch/mips/kernel/unaligned.c            |    5 +
 arch/mips/math-emu/cp1emu.c             |    3 +
 arch/mips/mm/fault.c                    |   11 +-
 arch/mips/oprofile/op_model_loongson2.c |   23 +-
 arch/mips/oprofile/op_model_mipsxx.c    |  164 +------
 arch/mips/oprofile/op_model_rm9000.c    |   16 +-
 14 files changed, 1797 insertions(+), 205 deletions(-)
 create mode 100644 arch/mips/include/asm/perf_event.h
 create mode 100644 arch/mips/include/asm/pmu.h
 create mode 100644 arch/mips/kernel/perf_event.c
 create mode 100644 arch/mips/kernel/perf_event_mipsxx.c


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