| To: | Thomas Bogendoerfer <tsbogend@alpha.franken.de> |
|---|---|
| Subject: | Re: [PATCH] MIPS: Calculate proper ebase value for 64-bit kernels |
| From: | Ralf Baechle <ralf@linux-mips.org> |
| Date: | Tue, 13 Apr 2010 18:16:10 +0100 |
| Cc: | Wu Zhangjin <wuzhangjin@gmail.com>, David Daney <ddaney@caviumnetworks.com>, linux-mips@linux-mips.org |
| In-reply-to: | <20100413073435.GA6371@alpha.franken.de> |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <1270585790-12730-1-git-send-email-ddaney@caviumnetworks.com> <1271135034.25797.41.camel@falcon> <20100413073435.GA6371@alpha.franken.de> |
| Sender: | linux-mips-bounce@linux-mips.org |
| User-agent: | Mutt/1.5.20 (2009-08-17) |
On Tue, Apr 13, 2010 at 09:34:38AM +0200, Thomas Bogendoerfer wrote: > On Tue, Apr 13, 2010 at 01:03:54PM +0800, Wu Zhangjin wrote: > > This patch have broken the support to the MIPS variants whose > > cpu_has_mips_r2 is 0 for the CAC_BASE and CKSEG0 is completely different > > in these MIPSs. > > I've checked R4k and R10k manulas and the exception base is at CKSEG0, so > about CPU we are talking ? And wouldn't it make for senso to have > an extra define for the exception base then ? C0_ebase's design was a short-sigthed only considering 32-bit processors. So the exception base is in CKSEG0 on every 64-bit processor, be it R2 or older. So yes, there is a bug as I've verified by testing but the patch is unfortunately incorrect. Ralf |
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