| To: | linux-mips@linux-mips.org, ralf@linux-mips.org |
|---|---|
| Subject: | [PATCH] MIPS: Calculate proper ebase value for 64-bit kernels |
| From: | David Daney <ddaney@caviumnetworks.com> |
| Date: | Tue, 6 Apr 2010 13:29:50 -0700 |
| Cc: | David Daney <ddaney@caviumnetworks.com> |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| Sender: | linux-mips-bounce@linux-mips.org |
The ebase is relative to CKSEG0 not CAC_BASE. On a 32-bit kernel they
are the same thing, for a 64-bit kernel they are not.
It happens to kind of work on a 64-bit kernel as they both reference
the same physical memory. However since the CPU uses the CKSEG0 base,
determining if a J instruction will reach always gives the wrong
result unless we use the same number the CPU uses.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
arch/mips/kernel/traps.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 7ce84bb..b122f76 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1706,7 +1706,7 @@ void __init trap_init(void)
ebase = (unsigned long)
__alloc_bootmem(size, 1 << fls(size), 0);
} else {
- ebase = CAC_BASE;
+ ebase = CKSEG0;
if (cpu_has_mips_r2)
ebase += (read_c0_ebase() & 0x3ffff000);
}
--
1.6.6.1
|
| <Prev in Thread] | Current Thread | [Next in Thread> |
|---|---|---|
| ||
| Previous by Date: | Re: [PATCH v3 1/3] Loongson-2F: Flush the branch target history such as BTB and RAS, Andreas Barth |
|---|---|
| Next by Date: | Hello My New Friend;, dickson Maria |
| Previous by Thread: | [PATCH] MIPS: Alchemy: db1200: remove custom wait implementation, Manuel Lauss |
| Next by Thread: | Re: [PATCH] MIPS: Calculate proper ebase value for 64-bit kernels, Ralf Baechle |
| Indexes: | [Date] [Thread] [Top] [All Lists] |