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[PATCH] MIPS: use compare_change_hazard in mips_next_event

To: Ralf Baechle <ralf@linux-mips.org>
Subject: [PATCH] MIPS: use compare_change_hazard in mips_next_event
From: Gabor Juhos <juhosg@openwrt.org>
Date: Sat, 27 Mar 2010 15:06:37 +0100
Cc: linux-mips@linux-mips.org, Gabor Juhos <juhosg@openwrt.org>
Original-recipient: rfc822;linux-mips@linux-mips.org
Sender: linux-mips-bounce@linux-mips.org
The compare_change_hazard() is used between write_c0_compare() and
read_c0_count() in c0_compare_int_usable(). The mips_next_event() uses
the same code sequence but without the compare_change_hazard call.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
---
 arch/mips/kernel/cevt-r4k.c |   33 +++++++++++++++++----------------
 1 files changed, 17 insertions(+), 16 deletions(-)

diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index 0b2450c..16cd116 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -16,6 +16,22 @@
 #include <asm/cevt-r4k.h>
 
 /*
+ * Compare interrupt can be routed and latched outside the core,
+ * so a single execution hazard barrier may not be enough to give
+ * it time to clear as seen in the Cause register.  4 time the
+ * pipeline depth seems reasonably conservative, and empirically
+ * works better in configurations with high CPU/bus clock ratios.
+ */
+
+#define compare_change_hazard() \
+       do { \
+               irq_disable_hazard(); \
+               irq_disable_hazard(); \
+               irq_disable_hazard(); \
+               irq_disable_hazard(); \
+       } while (0)
+
+/*
  * The SMTC Kernel for the 34K, 1004K, et. al. replaces several
  * of these routines with SMTC-specific variants.
  */
@@ -31,6 +47,7 @@ static int mips_next_event(unsigned long delta,
        cnt = read_c0_count();
        cnt += delta;
        write_c0_compare(cnt);
+       compare_change_hazard();
        res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0;
        return res;
 }
@@ -100,22 +117,6 @@ static int c0_compare_int_pending(void)
        return (read_c0_cause() >> cp0_compare_irq_shift) & (1ul << CAUSEB_IP);
 }
 
-/*
- * Compare interrupt can be routed and latched outside the core,
- * so a single execution hazard barrier may not be enough to give
- * it time to clear as seen in the Cause register.  4 time the
- * pipeline depth seems reasonably conservative, and empirically
- * works better in configurations with high CPU/bus clock ratios.
- */
-
-#define compare_change_hazard() \
-       do { \
-               irq_disable_hazard(); \
-               irq_disable_hazard(); \
-               irq_disable_hazard(); \
-               irq_disable_hazard(); \
-       } while (0)
-
 int c0_compare_int_usable(void)
 {
        unsigned int delta;
-- 
1.5.3.2


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