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Re: [PATCH 3/3] ide: move dcache flushing to generic ide code

To: sebastian@breakpoint.cc
Subject: Re: [PATCH 3/3] ide: move dcache flushing to generic ide code
From: David Miller <davem@davemloft.net>
Date: Sun, 28 Feb 2010 18:34:17 -0800 (PST)
Cc: ralf@linux-mips.org, linux-mips@linux-mips.org, linux-ide@vger.kernel.org
In-reply-to: <1267371341-16684-4-git-send-email-sebastian@breakpoint.cc>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <1267371341-16684-1-git-send-email-sebastian@breakpoint.cc> <1267371341-16684-4-git-send-email-sebastian@breakpoint.cc>
Sender: linux-mips-bounce@linux-mips.org
From: Sebastian Andrzej Siewior <sebastian@breakpoint.cc>
Date: Sun, 28 Feb 2010 16:35:41 +0100

> the pio callbacks are called with different kind of buffers. It could be
> a straight kernel addr, kernel stack or a kmaped highmem page.
> Some of this break the virt_to_page() assumptions.
> This patch moves the dcache flush from architecture code into generic
> ide code. ide_pio_bytes() is the only place where user pages might be
> written as far as I can see.
> The dcache flush is avoided in two cases:
> - data which is written to the device (i.e. they are comming from the
>   userland)

This needs a flush on sparc, otherwise an alias now exists in the
kernel side copy of the buffer.  The D-cache flush is intentionally
unconditional for PIO mode.  I definitely don't want to take the same
risks you guys seem to be willing to take for this optimization which
is of questionable value.

I also, intrinsically, really don't like these changes.

For one thing, you're optimizing PIO mode.

Secondly, IDE is in deep maintainence mode, if you want to optimize
cache flushing do it in the ATA layer.

Thanks.

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